Re: [PATCH v2] x86/cpufeatures: Enable new SSE/AVX/AVX512 cpu features

[Borislav Petkov]

On Mon, Oct 30, 2017 at 06:20:29PM -0700, Gayatri Kammela wrote:
> Add a few new SSE/AVX/AVX512 instruction groups/features for enumeration
> in /proc/cpuinfo: AVX512_VBMI2, GFNI, VAES, VPCLMULQDQ, AVX512_VNNI,
> AVX512_BITALG.
> 
> CPUID.(EAX=7,ECX=0):ECX[bit 6]  AVX512_VBMI2
> CPUID.(EAX=7,ECX=0):ECX[bit 8]  GFNI
> CPUID.(EAX=7,ECX=0):ECX[bit 9]  VAES
> CPUID.(EAX=7,ECX=0):ECX[bit 10] VPCLMULQDQ
> CPUID.(EAX=7,ECX=0):ECX[bit 11] AVX512_VNNI
> CPUID.(EAX=7,ECX=0):ECX[bit 12] AVX512_BITALG
> 
> Detailed information of cpuid bits for these features can be found
> in the Intel Architecture Instruction Set Extensions and Future Features
> Programming Interface document (refer to Table 1-1. and Table 1-2.).
> A copy of this document is available at
> https://bugzilla.kernel.org/show_bug.cgi?id=197239
> 
> Cc: Thomas Gleixner <tglx@xxxxxxxxxxxxx>
> Cc: Andi Kleen <andi.kleen@xxxxxxxxx>
> Cc: Ravi Shankar <ravi.v.shankar@xxxxxxxxx>
> Cc: Fenghua Yu <fenghua.yu@xxxxxxxxx>
> Cc: Ricardo Neri <ricardo.neri@xxxxxxxxx>
> Cc: Yang Zhong <yang.zhong@xxxxxxxxx>
> Signed-off-by: Gayatri Kammela <gayatri.kammela@xxxxxxxxx>
> ---
> Changes since v1:
> 1) Rebased against the tip tree and so removed all the setup_clear flags
> 
>  arch/x86/include/asm/cpufeatures.h | 6 ++++++
>  arch/x86/kernel/cpu/cpuid-deps.c   | 6 ++++++
>  2 files changed, 12 insertions(+)
> 
> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> index 401a70992060..b0556f882aa8 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -299,6 +299,12 @@
>  #define X86_FEATURE_AVX512VBMI  (16*32+ 1) /* AVX512 Vector Bit Manipulation instructions*/

So we have previous AVX512 feature bits which do not separate AVX512
with a "_" but the new ones do. I think we should unify this and the SDM
should be fixed too.

-- 
Regards/Gruss,
    Boris.

Good mailing practices for 400: avoid top-posting and trim the reply.