Re: [PATCH] MIPS: Fix exception entry when CONFIG_EVA enabled

From: Matt Redfearn
Date: Wed Nov 15 2017 - 05:33:04 EST




On 13/11/17 10:47, Maciej W. Rozycki wrote:
On Tue, 31 Oct 2017, James Hogan wrote:

I looked this over pretty carefully and it looks correct to me. It
makes no difference
in the instructions generated by the non-EVA case. I shouldn't have
missed this :(.

Reviewed-by: Corey Minyard <cminyard@xxxxxxxxxx>

Yeh, having stared at it for a little while it looks correct to me too.

Reviewed-by: James Hogan <jhogan@xxxxxxxxxx>

How about getting rid of the `noreorder' mode and the manually scheduled
delay slot here altogether though, as I outlined?

Maciej


Hi Maciej,

I like the change you propose, however I can't coax GAS to reorder the instructions appropriately. With this patch on top of 4.14:

--- a/arch/mips/include/asm/stackframe.h
+++ b/arch/mips/include/asm/stackframe.h
@@ -195,14 +195,16 @@
.set push
.set noat
.set reorder
- mfc0 k0, CP0_STATUS
- sll k0, 3 /* extract cu0 bit */
- .set noreorder
- bltz k0, 8f
- move k0, sp
+ mfc0 k1, CP0_STATUS
+ sll k1, 3 /* extract cu0 bit */
+
+ move k0, sp
.if \docfi
.cfi_register sp, k0
.endif
+
+ bltz k1, 8f
+
#ifdef CONFIG_EVA
/*
* Flush interAptiv's Return Prediction Stack (RPS) by writing
@@ -228,7 +230,6 @@
MFC0 k0, CP0_ENTRYHI
MTC0 k0, CP0_ENTRYHI
#endif
- .set reorder
/* Called from user mode, new stack. */
get_saved_sp docfi=\docfi tosp=1
8:


The generated assembly is:

80405d00 <handle_int>:
80405d00: 401b6000 mfc0 k1,c0_status
80405d04: 001bd8c0 sll k1,k1,0x3
80405d08: 03a0d025 move k0,sp
80405d0c: 07600007 bltz k1,80405d2c <handle_int+0x2c>
80405d10: 00000000 nop
80405d14: 401a2000 mfc0 k0,c0_context

Apparently GAS has not been able to reorder the move into the branch delay slot for some reason. Any ideas?

Thanks,
Matt