Re: [PATCH v6 04/11] x86: define IA32_FEATUE_CONTROL.SGX_LC

[Sean Christopherson]

On Tue, 2017-11-28 at 23:24 +0200, Jarkko Sakkinen wrote:
> On Tue, Nov 28, 2017 at 10:53:24PM +0200, Jarkko Sakkinen wrote:
> > 
> > > 
> > > So, maybe something like this?
> > > 
> > > Â Â After SGX is activated[1] the IA32_SGXLEPUBKEYHASHn MSRs are writable
> > > Â Â if and only if SGX_LC is set in the IA32_FEATURE_CONTROL MSR and the
> > > Â Â IA32_FEATURE_CONTROL MSR is locked, otherwise they are read-only.
> > > 
> > > Â Â For example, firmware can allow the OS to change the launch enclave
> > > Â Â root key by setting IA32_FEATURE_CONTROL.SGX_LC, and thus give the
> > > Â Â OS complete control over the enclaves it runs. ÂAlternatively,
> > > Â Â firmware can clear IA32_FEATURE_CONTROL.SGX_LC to lock down the root
> > > Â Â key and restrict the OS to running enclaves signed with the root key
> > > Â Â or whitelisted/trusted by a launch enclave (which must be signed with
> > > Â Â the root key).
> > > 
> > > Â Â [1] SGX related bits in IA32_FEATURE_CONTROL cannot be set until SGX
> > > Â Â Â Â is activated, e.g. by firmware. ÂSGX activation is triggered by
> > > Â Â Â Â setting bit 0 in MSR 0x7a. ÂUntil SGX is activated, the LE hash
> > > Â Â Â Â MSRs are writable, e.g. to allow firmware to lock down the LE
> > > Â Â Â Â root key with a non-Intel value.
> > Thanks I'll use this as a basis and move most of the crappy commit
> > message to the commit (with some editing) that defines the MSRs.
> Not sure after all if I'm following this.
> 
> IA32_FEATURE_CONTROL[17] contols whether the MSRs are writable or not
> after the feature control MSR is locked. SGX_LC means just that the
> CPU supports the launch configuration.
> 
> /Jarkko

My comments were referring to improving the commit message for defining
IA32_FEATURE_CONTROL.SGX_LC, i.e. bit 17, not the CPUID bit.