Re: [PATCH v2] ASOC: wm8960: Add multiple MCLK frequency support

[Charles Keepax]

On Fri, Dec 22, 2017 at 06:40:04PM +0800, chen liu wrote:
> 2017-12-22 0:48 GMT+08:00 Charles Keepax <ckeepax@xxxxxxxxxxxxxxxxxxxxx>:
> > On Tue, Dec 19, 2017 at 02:19:48PM +0800, chen liu wrote:
> >> 2017-12-18 19:55 GMT+08:00 Charles Keepax <ckeepax@xxxxxxxxxxxxxxxxxxxxx>:
> >> > On Mon, Dec 18, 2017 at 07:32:41PM +0800, chen liu wrote:
> >> > > 2017-12-18 17:31 GMT+08:00 Charles Keepax <ckeepax@xxxxxxxxxxxxxxxxxxxxx
> >> > > > On Fri, Dec 15, 2017 at 09:07:15PM +0800, chen liu wrote:
> >> > > > > 2017-12-15 0:19 GMT+08:00 Charles Keepax <
> >> > ckeepax@xxxxxxxxxxxxxxxxxxxxx
> >> > > > > > On Wed, Dec 13, 2017 at 08:37:30PM +0800, Chen.Liu wrote:
> 
> > One thing I don't understand though is it looks like the freq_out
> > returned from wm8960_configure_pll should already be taking the
> > SYSCLK_DIV into account:
> >
> > for (j = 0; j < ARRAY_SIZE(dac_divs); ++j) {
> >         sysclk = lrclk * dac_divs[j];
> >         freq_out = sysclk * sysclk_divs[i];
> >
> > So if lrclk=44100, j=0, i=2 which I believe is the case in
> > question we should get:
> >
> > sysclk = 44100 * 256 = 11.2896MHz
> > freq_out = 11.2896MHz * 2 = 22.5792MHz
> >
> > So when wm8960_configure_pll returns i=2 then it should also be
> > setting freq_out as 22.5792MHz. So you final call there to
> > wm8960_set_pll should be:
> 
> This problem seems to affect only the clock frequency configured in
> manual mode.

Ok cool, so you are using manual mode :-)

> 
> Because i'm directly calling the 'snd_soc_dai_set_pll' function in the
> machine driver,the driver will  prompts ''WM8960 PLL: Unsupported N"
> error message.
> The following code is part of how i configured the clock frequency in the
> machine driver:
> ======================================================
> +       if (params_rate(params) == 44100)
> +               pll_out = 11289600;
> +       else
> +               pll_out = 12288000;
> +
> +       ret = snd_soc_dai_set_pll(codec_dai, WM8960_SYSCLK_PLL, 0,
> +
> data->clk_frequency, pll_out);
> 
> ======================================================
> 
> On the other hand,i think if the codec support these MCLK clock frequency
> in the manual,so no matter use manual mode and automatic mode to
> configure the clock frequency,the driver prompt errors is very bad.

The original intention using the manual path was that you would
set the clock divider manually using snd_soc_dai_set_clkdiv:

snd_soc_dai_set_clkdiv(codec_dai, WM8960_SYSCLKDIV, 2);

And then pass an adjusted frequency to your call to
snd_soc_dai_set_pll:

ret = snd_soc_dai_set_pll(codec_dai, WM8960_SYSCLK_PLL, 0,
                          data->clk_frequency, pll_out / 2);

So you could do that and that should give you everything working
using the manual mode.

Now Mark does point out that we probably should be looking to
replace set_clkdiv since its use is discouraged. Now if you want
to proceed down that path your patch will need some work.

The problem is you are duplicating code that basically already
exists in wm8960_configure_pll and both sets of code are running
when using the automatic path. I am not very keen on that, really
you need to look at starting to combine the code for both paths a
little more. Such that there is one place in the code that is
calculating and setting the sysclk div.

Thanks,
Charles