On Thu, Apr 05, 2018 at 04:44:16PM +0300, Sergey Suloev wrote:
On 04/05/2018 04:17 PM, Mark Brown wrote:Because you're not supposed to have a transfer larger than the FIFO,
On Thu, Apr 05, 2018 at 12:59:35PM +0300, Sergey Suloev wrote:Well, normally yes, but this is not the case with the hardware that I own.
On 04/05/2018 12:19 PM, Maxime Ripard wrote:Are you positive about that? Normally you can add things to hardware
The point of that patch was precisely to allow to send more data thanI am sorry, but you can't. That's a hardware limitation.
the FIFO. You're breaking that behaviour without any justification,
and this is not ok.
FIFOs while they're being drained so so long as you can keep data
flowing in at least as fast as it's being consumed.
My a20 (BPiM1+) and a31 (BPiM2) boards behaves differently. With a transfer
larger than FIFO then TC interrupt never happens.
but to have to setup at first a transfer the size of the FIFO, and
then when it's (or starts to be) depleted, fill it up again.
That's the point of the patch you're reverting, and if it doesn't
work, you should make it work and not simply revert it.