Re: [PATCH v2 2/2] parisc: define stronger ordering for the default readX()
From: Sinan Kaya
Date: Tue Apr 17 2018 - 14:29:08 EST
On 4/17/2018 11:55 AM, James Bottomley wrote:
> On Tue, 2018-04-17 at 10:13 -0400, Sinan Kaya wrote:
>> Hi James,
>>> Perhaps if you gave an example of the actual problem you're trying
>>> to fix we could assess if it affects parisc.
>> Let me clarify myself here. Maybe, there is a better solution.
>> /* assign ownership */
>> desc->status = DEVICE_OWN;
>> /* notify device of new descriptors */
>> writel(DESC_NOTIFY, doorbell);
>> The difference between writel() and writel_relax() is writel()
>> guarantees memory transactions to be flushed to the device before the
>> register write.
> Um, no it doesn't, at least not in PCI. It guarantees the write will
> be issued by the memory system, but it may still be cached (called
> posting) in the PCI bridge. So it doesn't guarantee the write reaches
> the device by the time it returns.
The correct terminology here would be to use observability. Yes, it can be
cached in whatever part of the system for some amount of time as long as
PCI device sees it in the correct order.
Let's do this exercise.
1. OS writes to memory for some descriptor update
2. OS writes to the device via writel to hit a doorbell
3. Device comes and fetches the memory contents for the descriptor
writel() of PA-RISC needs to ensure that 3. cannot bypass 1. This is typically
done by a write barrier embedded into the writel() on relaxed architectures.
>> writel_relaxed() does not provide any guarantees about the memory
>> and IO operations.
>> Similarly, readl() provides following code to observe the DMA result
>> while readl_relaxed() does not provide this guarantee.
> Right, the relaxed operator provides no guarantee of ordering between
> the memory and IO domains. However, it's only really a problem on
> multiple memory controller systems (i.e. NUMA). Parisc (except
> superdome, which we don't support) doesn't have this problem. We also
> turn of CPU stream reordering, so compile order is retire order on our
> CPUs (which makes life a lot simpler).
Good to know.
>> Ideally, you want to embed rmb() and wmb() into the writel() and
>> readl() to provide this guarantee.
>> PA-RISC doesn't seem to support neither one of the barrier types. If
>> you are familiar with the architecture, maybe you could guide us
>> Is __raw_writeX() enough to provide this guarantee for this
> Well, with the volatile address it is.
> The current implementations provide the expected semantics: namely the
> position in the instruction stream is compile (retire) ordered and
> issued from memory once retired. We still do have the write posting
> problem, but you'll find additional reads in the drivers to flush the
> posted writes, so I don't actually believe we need anything changing.
OK. I'll withdraw my patch. I'm just trying to ensure that all architectures
support writel() semantics. There is an attempt to remove unnecessary
write barriers from the drivers directory between the descriptor update and
Just checking that PA-RISC won't break after this.
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