Re: [PATCH] clk-si544: Properly round requested frequency to nearest match

From: Mike Looijmans
Date: Fri Jun 01 2018 - 03:19:18 EST

ïOn 31-05-18 17:34, Stephen Boyd wrote:
Quoting Mike Looijmans (2018-05-31 07:03:55)
The si544 driver had a rounding problem that using the result of clk_round_rate
may set the clock to yet another rate, for example:
clk_round_rate(195000000) = 194999999
clk_round_rate(194999999) = 194999998

Clients would expect that after clk_set_rate(clk, freq2=clk_round_rate(clk, freq)) the
chip will be running at exactly freq2.

The problem was in the calculation of the feedback divider, it was always rounded
down instead of to the nearest possible VCO value.

After this change, the following holds true for any supported frequency:
actual_freq = clk_round_rate(clk, freq);
clk_set_rate(clk, actual_freq);
clk_round_rate(clk, actual_freq) == actual_freq && clk_get_rate(clk) == actual_freq

Signed-off-by: Mike Looijmans <mike.looijmans@xxxxxxxx>

Any fixes tag? I can slap

Fixes: 953cc3e81170 ("clk: Add driver for the si544 clock generator chip")

on to the patch here.

I think that would be good, yes. Slap it on.

Kind regards,

Mike Looijmans
System Expert

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