Re: [PATCH V2 11/19] csky: Atomic operations
From: Guo Ren
Date: Sat Jul 07 2018 - 20:44:42 EST
On Sat, Jul 07, 2018 at 09:54:37PM +0200, Andrea Parri wrote:
> Hi Guo,
> On Sat, Jul 07, 2018 at 03:42:10PM +0800, Guo Ren wrote:
> > On Fri, Jul 06, 2018 at 01:56:14PM +0200, Peter Zijlstra wrote:
> > > CPU0 CPU1
> > >
> > > r1 = READ_ONCE(x); WRITE_ONCE(y, 1);
> > > r2 = xchg(&y, 2); smp_store_release(&x, 1);
> > >
> > > must not allow: r1==1 && r2==0
> > CPU1 smp_store_release could be finished before WRITE_ONCE, so r1=1 &&
> > r2=0?
> The emphasis is on the "must": your implementation __must__ prevent this
> from happening (say, by inserting memory barriers in smp_store_release());
> if your implementation allows the state (r1==1 && r2==0), then the imple-
> mentation is incorrect.
Ok, Got it.
> I'd suggest you have a look at the Linux-kernel memory consistency model
> documentation and the associated tools, starting with:
Thx for the tips.
> (and please do not hesitate to ask questions about them, if something is
I'll. Thx again.