Re: [PATCH v6 00/10] Add the I3C subsystem

[Arnd Bergmann]

On Fri, Jul 20, 2018 at 1:13 PM, Peter Rosin <peda@xxxxxxxxxx> wrote:
> On 2018-07-20 12:57, Arnd Bergmann wrote:
>> * What I understand from reading i2c-demux-pinctrl.c, a slave device
>>   will only ever be observable from one master at a time, when you
>>   switch over, all children get removed on one master and added to
>>   the other one, to be probed again by their respective drivers.
>>   I can see this as a useful feature on i3c as well, in particular to
>>   deal with the situation where we have i2c slaves connected to a
>>   pinmux that can switch them between an i3c master and an
>>   i2c-only master (possibly a gpio based one). That particular use
>>   case however doesn't seem to fix well in the current code, which
>>   is structure around i3c buses.
>
> It's pretty easy to come up with examples where this reprobing is
> not desirable at all. E.g. if one of the involved I2C devices is
> a HDMI encoder (I have a TDA19988 here) sitting in the middle of the
> graphics pipeline. Blink-blink on the screen because some *other*
> unrelated device needed to be accessed by an alternative master. Not
> pretty.

Agreed, we definitely don't want to reprobe all devices during normal
operation for i3c master handover.

What is the least contrived use case that you can think of where we
would want to use one master to talk to one device on the bus,
but another master to talk to another device on the same bus?
I still hope that we can decide that this is not a useful scenario
at all.

If we find a case in which it is needed, we could still deal with it
like this:
- enumerate all slaves connected to the bus for each of the
  two masters
- mark each slave as status="enabled" in at most one of the
  buses, and as disabled everywhere else
- Use dynamic handover according to the bus protocol to
  switch masters without having Linux even know that the
  two buses are shared.

That scenario would then fall completely into the "secondary
master handover" category but require no special handling
in the i3c layer beyond what we need for secondary masters
that are managed by something outside of the kernel's
score (a microcontroller, firmware, ...).

       Arnd