Re: [PATCH 02/11] dt-bindings: Add an enable method to RISC-V

From: Rob Herring
Date: Wed Aug 08 2018 - 10:43:17 EST


On Thu, Aug 2, 2018 at 5:50 AM Christoph Hellwig <hch@xxxxxx> wrote:
>
> From: Palmer Dabbelt <palmer@xxxxxxxxxx>
>
> RISC-V doesn't currently specify a mechanism for enabling or disabling
> CPUs. Instead, we assume that all CPUs are enabled on boot, and if
> someone wants to save power we instead put a CPU to sleep via a WFI
> loop. Future systems may have an explicit mechanism for putting a CPU
> to sleep, so we're standardizing the device tree entry for when that
> happens.
>
> We're not defining a spin-table based interface to the firmware, as the
> plan is to handle this entirely within the kernel instead.
>
> Signed-off-by: Palmer Dabbelt <palmer@xxxxxxxxxx>
> Signed-off-by: Christoph Hellwig <hch@xxxxxx>
> ---
> Documentation/devicetree/bindings/riscv/cpus.txt | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.txt b/Documentation/devicetree/bindings/riscv/cpus.txt
> index b0b038d6c406..6aa9cd075a5b 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.txt
> +++ b/Documentation/devicetree/bindings/riscv/cpus.txt
> @@ -82,6 +82,15 @@ described below.
> Value type: <string>
> Definition: Contains the RISC-V ISA string of this hart. These
> ISA strings are defined by the RISC-V ISA manual.
> + - cpu-enable-method:

Something wrong with "enable-method" as defined in the DT spec[1]?

> + Usage: optional
> + Value type: <stringlist>
> + Definition: When absent, default is either "always-disabled"
> + "always-enabled", depending on the current state
> + of the CPU.
> + Must be one of:
> + * "always-disabled": This CPU cannot be enabled.
> + * "always-enabled": This CPU cannot be disabled.

To follow the spec, 'enable-method' should simply not be present in
the always-enabled case. I think the always disabled case should be
handled with:

status = "disabled";
enable-method = "none";

With "none" needing to be added to the spec.

[1] https://github.com/devicetree-org/devicetree-specification/blob/master/source/devicenodes.rst#general-properties-of-cpuscpu-nodes