On Tue, Aug 14, 2018 at 02:30:02PM +0530, dkota@xxxxxxxxxxxxxx wrote:
On 2018-08-10 22:16, Mark Brown wrote:
> On Fri, Aug 10, 2018 at 09:59:46PM +0530, dkota@xxxxxxxxxxxxxx wrote:
> > delay_usecs is for inter-transfer delays within a message rather than
> > after the initial chip select assert (it can be used to keep chip
> > select
> > asserted for longer after the final transfer too). Obviously this is
> > also something that shouldn't be configured in a driver specific
> > fashion.
> Hmmm ok, so you mean don't send these as controller_data, rather add
> members to the spi_device struct ?
spi_cs_clk_delay -> Adds Delay from CS line toggle to Clock line toggle
spi_inter_words_delay -> Adds inter-word delay for each transfer.
Could you please provide more information on accommodating these
parameters in SPI core structures like spi_device or spi_transfer? Why
because these are very
specific to Qualcomm SPI GENI controller.
I'm not sure what specific information you're looking for here - these
things are not obviously specific to your controller, I'm even aware of
other controllers which can do them.
If we define them in spi core framework structures, SPI Slave driver will
program and expect it in the SPI transfers.
+ mas->cur_speed_hz = spi_slv->max_speed_hz;
Why can't you use clk_get_rate() instead? Or call clk_set_rate() with
the rate you want the master clk to run at and then divide that down
> Not sure I follow, the intention is to run the controller clock based on
> the slave's max frequency.
That's good. The problem I see is that we have to specify the max
frequency in the controller/bus node, and also in the child/slave
It should only need to be specified in the slave node, so making the
cur_speed_hz equal the max_speed_hz is problematic. The current speed
the master should be determined by calling clk_get_rate().
We don't require that the slaves all individually set a speed since it
gets a bit redundant, it should be enough to just use the default the
controller provides. A bigger problem with this is that the driver
never see a transfer which doesn't explicitly have a speed set as the
core will ensure something is set, open coding this logic in every
driver would obviously be tiresome.