Re: [Xen-devel] [PATCH v2 2/2] x86/pae: use 64 bit atomic xchg function in native_ptep_get_and_clear
From: Jan Beulich
Date: Tue Aug 21 2018 - 11:57:46 EST
>>> On 21.08.18 at 17:37, <jgross@xxxxxxxx> wrote:
> Using only 32-bit writes for the pte will result in an intermediate
> L1TF vulnerable PTE. When running as a Xen PV guest this will at once
> switch the guest to shadow mode resulting in a loss of performance.
> Use arch_atomic64_xchg() instead which will perform the requested
> operation atomically with all 64 bits.
> Some performance considerations according to:
> The main number should be the latency, as there is no tight loop around
> "lock cmpxchg8b" has a latency of 20 cycles, while "lock xchg" (with a
> memory operand) isn't mentioned in that document. "lock xadd" (with xadd
> having 3 cycles less latency than xchg) has a latency of 11, so we can
> assume a latency of 14 for "lock xchg".
> Signed-off-by: Juergen Gross <jgross@xxxxxxxx>
Reviewed-by: Jan Beulich <jbeulich@xxxxxxxx>
with one further remark:
> @@ -150,10 +152,7 @@ static inline pte_t native_ptep_get_and_clear(pte_t *ptep)
> pte_t res;
> - /* xchg acts as a barrier before the setting of the high bits */
> - res.pte_low = xchg(&ptep->pte_low, 0);
> - res.pte_high = ptep->pte_high;
> - ptep->pte_high = 0;
> + res.pte = (pteval_t)arch_atomic64_xchg((atomic64_t *)ptep, 0);
Is the cast on the return value really needed here?