Re: [PATCH 00/12] Avoid synchronous TLB invalidation for intermediate page-table entries on arm64
From: Peter Zijlstra
Date: Fri Aug 31 2018 - 07:20:36 EST
On Fri, Aug 31, 2018 at 12:12:48PM +0100, Will Deacon wrote:
> On Fri, Aug 31, 2018 at 12:49:45PM +0200, Peter Zijlstra wrote:
> > On Fri, Aug 31, 2018 at 08:32:34PM +1000, Nicholas Piggin wrote:
> > > Oh gee, I suppose. powerpc hash is kind of interesting because it's
> > > crazy, Aneesh knows that code a lot better than I do. radix modulo
> > > some minor details of exact instructions is fairly like x86
> > The whole TLB broadcast vs explicit IPIs is a fairly big difference in
> > my book.
> > Anyway, have you guys tried the explicit IPI approach? Depending on how
> > IPIs are routed vs broadcasts it might save a little bus traffic. No
> > point in getting all CPUs to process the TLBI when there's only a hand
> > full that really need it.
> > OTOH, I suppose the broadcast thing has been optimized to death on the
> > hardware side, so who knows..
> You also can't IPI an IOMMU or a GPU ;)
Oh, right you are. I suppose that is why x86-iommu is using those mmu_notifiers.