Hi Lina,I should have removed this paragraph. This is not relevant to the
Quoting Lina Iyer (2018-10-10 17:29:58)
QCOM SoC's that have Power Domain Controller (PDC) chip in the always-on
domain can wakeup the SoC, when interrupts and GPIOs are routed to its
interrupt controller. Only select GPIOs that are deemed wakeup capable
are routed to specific PDC pins. During low power state, the pinmux
interrupt controller may be non-functional but the PDC would be. The PDC
can detect the wakeup GPIO is triggered and bring the TLMM to an
Interrupts that are level triggered will be detected at the TLMM when
the controller becomes operational. Edge interrupts however need to be
Request the corresponding PDC IRQ, when the GPIO is requested as an IRQ,
but keep it disabled. During suspend, we can enable the PDC IRQ instead
of the GPIO IRQ, which may or not be detected.
This is exactly what this patch does. We dont want to use the GPIO IRQSigned-off-by: Lina Iyer <ilina@xxxxxxxxxxxxxx>
So we may need
to change #4 up above to always allocate the irq from PDC and somehow
communicate that the irq is wakeup capable in PDC back to the TLMM
driver so TLMM knows to keep the irq masked in the hardware forever.
That way it can't cause the summary irq line to trigger in addition to
the PDC one. Given that we have allocation hooks with domain hierarchy
it may be easy enough to remove TLMM irqs from the summary irq domain
when they can be allocated from the parent PDC domain.