RE: [PATCH v7 11/13] arch/x86: Introduce QOS feature for AMD

[Moger, Babu]

Fenghua,

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> Subject: RE: [PATCH v7 11/13] arch/x86: Introduce QOS feature for AMD
> 
> > From: Moger, Babu [mailto:Babu.Moger@xxxxxxx]
> > Subject: [PATCH v7 11/13] arch/x86: Introduce QOS feature for AMD
> > The specification for this feature is available at
> > https://developer.amd.com/wp-content/resources/56375.pdf
> 
> > +bool cbm_validate_amd(char *buf, u32 *data, struct rdt_resource *r) {
> > +	if (val > r->default_ctrl) {
> > +		rdt_last_cmd_puts("mask out of range\n");
> > +		return false;
> > +	}
> 
> If val is zero, then this closid cannot allocate any cache line.
> 
> I'm wondering: does that mean the tasks running with this closid directly
> access memory without cache? Is there any usage for this situation?

I would think any memory access has to happen via cache only.  But
I am not sure about the usage of this situation. Will check on that.
Will post if I get any more information. But I can say that it is
allowed to have mask as zero. Looking at the specs
https://developer.amd.com/wp-content/resources/56375.pdf

The bits which are set in the various L3_MASK_n registers do not have to be
contiguous and may overlap in any desired combination. If an L3_MASK_n
register is programmed with all 0's, that COS will be prevented from allocating
any lines in the L3 cache. At reset, all L3_MASK_n registers are initialized to all
1's, allowing all processors to use the entire L3 cache accessible to them.

> 
> Thanks.
> 
> -Fenghua