Re: [PATCH 10/13] arm64: dts: qcom: qcs404: Add HFPLL node

[Stephen Boyd]

Quoting Bjorn Andersson (2019-01-16 22:38:04)
> On Mon 17 Dec 11:39 PST 2018, Stephen Boyd wrote:
> 
> > Quoting Jorge Ramirez-Ortiz (2018-12-17 01:46:27)
> > > The high frequency pll functionality is required to enable CPU
> > > frequency scaling operation.
> > > 
> > > Co-developed-by: Niklas Cassel <niklas.cassel@xxxxxxxxxx>
> > > Signed-off-by: Niklas Cassel <niklas.cassel@xxxxxxxxxx>
> > > Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@xxxxxxxxxx>
> > > ---
> > >  arch/arm64/boot/dts/qcom/qcs404.dtsi | 9 +++++++++
> > >  1 file changed, 9 insertions(+)
> > > 
> > > diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
> > > index 4594fea7..ec3f6c7 100644
> > > --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
> > > +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
> > > @@ -375,6 +375,15 @@
> > >                         #mbox-cells = <1>;
> > >                 };
> > >  
> > > +               apcs_hfpll: clock-controller@0b016000 {
> > 
> > Drop leading 0 on unit address please.
> > 
> > > +                       compatible = "qcom,hfpll";
> > > +                       reg = <0x0b016000 0x30>;
> > 
> > Wow that is small!
> > 
> 
> I double checked and it's actually 0x34, but the last register is
> protected.
> 

Ok, so then it should be 0x34? I don't think we've left out protected
registers from the size before.