Re: [PATCH] clk: ingenic: jz4740: Fix gating of UDC clock

From: Paul Cercueil
Date: Tue Jan 29 2019 - 14:22:47 EST


Le mar. 29 janv. 2019 à 15:13, Stephen Boyd <sboyd@xxxxxxxxxx> a écrit :
Quoting Paul Cercueil (2019-01-25 11:24:58)

On Fri, Jan 25, 2019 at 3:55 PM, Stephen Boyd <sboyd@xxxxxxxxxx> wrote:
> Quoting Paul Cercueil (2019-01-25 07:34:36)
>> The UDC clock is gated when the bit is cleared, not when it is set.
>> Signed-off-by: Paul Cercueil <paul@xxxxxxxxxxxxxxx
>> <mailto:paul@xxxxxxxxxxxxxxx>>
>> Tested-by: Artur Rojek <contact@xxxxxxxxxxxxxx
>> <mailto:contact@xxxxxxxxxxxxxx>>
>> ---
> Any Fixes tag for this?

Fixes: 2b555a4b9cae

Should I resend?

No need to resend. Is this fixing something that's broken in the v5.0-rc
series? I'm trying to understand if this is a critical fix or a
non-critical fix that can bake until the next release cycle.

It's been broken for one year and nobody noticed, it can wait for 5.1.