Quoting Paul Cercueil (2019-01-25 11:24:58)
On Fri, Jan 25, 2019 at 3:55 PM, Stephen Boyd <sboyd@xxxxxxxxxx> wrote:
> Quoting Paul Cercueil (2019-01-25 07:34:36)
>> The UDC clock is gated when the bit is cleared, not when it is set.
>> Signed-off-by: Paul Cercueil <paul@xxxxxxxxxxxxxxx
>> Tested-by: Artur Rojek <contact@xxxxxxxxxxxxxx
> Any Fixes tag for this?
Should I resend?
No need to resend. Is this fixing something that's broken in the v5.0-rc
series? I'm trying to understand if this is a critical fix or a
non-critical fix that can bake until the next release cycle.