[GIT PULL] RISC-V Patches for the 5.1 Merge Window, Part 1

From: Palmer Dabbelt
Date: Tue Mar 05 2019 - 16:42:20 EST

The following changes since commit 41fb9d54f12b87fb1f670653e95d34668a08e8ee:

Revert "RISC-V: Make BSS section as the last section in vmlinux.lds.S" (2019-02-11 15:24:45 -0800)

are available in the Git repository at:

git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux.git tags/riscv-for-linus-5.1-mw0

for you to fetch changes up to 13fd5de06514458eb320188b7a815d65696efd99:

RISC-V: Fixmap support and MM cleanups (2019-03-04 11:47:04 -0800)

RISC-V Patches for the 5.1 Merge Window, Part 1

This contains the vast majority of the RISC-V patches for this merge
window. It includes:

* A handful of cleanups to our kernel prints, most of which are things I
should have caught the first time.
* We now provide an HWCAP that contains the ISA extensions that all
enabled processors support, as supposed to just looking at the first
enabled processor.
* We no longer spin forever waiting for all harts to boot.
* A fixmap implementation, which is coupled to some cleanups in our MM

The only outstanding patches I know of right now are Vincent Chen's
patches to fix c.ebreak handling in the kernel, the v2 of which was
posted this morning. I'd like those in the MW, but I didn't want to
hold up everything else. The patch set is based on top of my last fixes
submission, but I've tested it with a conflict-free merge from v5.0.
I'm doing this rather than my "just go rebase everything" flow due to a
discussion with Linus, but if I misunderstood then just let me know and
I'll do something else. It's also the first time I've taken a PR into
my own tree, so let me know if I screwed that one up.

I've used my standard testing flow (QEMU in Fedora), but now that we're
starting to get the kernel in better shape I think it's time to impose
some more testing here -- specifically I'm going to require that patches
boot on the HiFive Unleashed because we're getting to the point where we
can actually expect that to work. I haven't done that for this tag, but
I'm going to do it for future ones.

I know the board is a bit expensive and not everyone has one, but if
I've sent you a free one and your patches break the boot then I'm going
to yell at you :). If you don't have one then please indicate how you
tested in your cover letter, and if you have a board then please add
your Tested-by to patches if they work for your testing flow.

Andreas Schwab (1):
arch: riscv: fix logic error in parse_dtb

Anup Patel (5):
RISC-V: Setup init_mm before parse_early_param()
RISC-V: Move setup_bootmem() to mm/init.c
RISC-V: Move setup_vm() to mm/init.c
RISC-V: Implement compile-time fixed mappings
RISC-V: Free-up initrd in free_initrd_mem()

Atish Patra (6):
RISC-V: Do not wait indefinitely in __cpu_up
RISC-V: Move cpuid to hartid mapping to SMP.
RISC-V: Remove NR_CPUs check during hartid search from DT
RISC-V: Allow hartid-to-cpuid function to fail.
RISC-V: Compare cpuid with NR_CPUS before mapping.
RISC-V: Assign hwcap as per comman capabilities.

Christoph Hellwig (1):
riscv: remove the HAVE_KPROBES option

Johan Hovold (5):
riscv: add missing newlines to printk messages
riscv: use pr_info and friends
riscv: fix riscv_of_processor_hartid() comment
riscv: treat cpu devicetree nodes without status as enabled
riscv: use for_each_of_cpu_node iterator

Palmer Dabbelt (1):
RISC-V: Fixmap support and MM cleanups

arch/riscv/Kconfig | 6 +-
arch/riscv/include/asm/fixmap.h | 44 +++++++++++
arch/riscv/include/asm/pgtable.h | 1 +
arch/riscv/include/asm/smp.h | 18 +++--
arch/riscv/kernel/cpu.c | 30 +++-----
arch/riscv/kernel/cpufeature.c | 48 ++++++------
arch/riscv/kernel/ftrace.c | 2 +-
arch/riscv/kernel/setup.c | 141 ++---------------------------------
arch/riscv/kernel/smp.c | 10 ++-
arch/riscv/kernel/smpboot.c | 24 ++++--
arch/riscv/mm/init.c | 156 ++++++++++++++++++++++++++++++++++++++-
11 files changed, 287 insertions(+), 193 deletions(-)
create mode 100644 arch/riscv/include/asm/fixmap.h