Re: [PATCH] RISC-V: Implement ASID allocator

From: Anup Patel
Date: Wed Mar 27 2019 - 07:42:28 EST

On Wed, Mar 27, 2019 at 4:57 PM Gary Guo <gary@xxxxxxxxxxx> wrote:
> Hi Anup,
> This won't work in an actual hardware with ASID support. There're more

Can you elaborate why?

This implementation is based on Linux ARM64 ASID allocator which is
tested for large number of CPUs on real HW.

> interactions with TLB flushes that need to be considered. You won't see

Yap, already considered. Please point me to unhandled case.

> this on both QEMU and SiFive board, as QEMU does not have ASID, so it
> pretends that ASID is supported by just flushing its TLB everytime you

Nope, it does not. It detects whether ASID is supported or not. If supported
it will also figure-out number of ASID bits supported by HW.

SiFive board does not have ASID bits so this implementation successfully
detects that number of ASID bits are 0 and fallbacks to original way of
local TLB flushes.

> change sptbr. I suspect the performance gain you see is just due to
> saved TLB flush as TLB flush is super expensive in QEMU (all translation
> block jumps need to be cleared).

Yes, performance gain is due to saved TLB flushes.

On HW which supports ASID bits, we will see more performance

> I have my version here I
> haven't done code cleanups yet, but this version has correctness of its
> ASID code tested on our TLB simulator tool (which unfortunately I can't
> share right now as it involves with unpublished works).

Except few minor differences. You version of ASID allocator is same as
mine. In fact there are lot of similar code framgements in your version
compared to Linux ARM64 as well. I am sure this patch will work for you.

> In fact my submit my previous patch series exactly as the basis of this
> patch.

This patch is based your patch series so I suggest you take this patch
and try it on your simulator.

Suggestions and improvements to this patch are welcomed.

I would be happy if you can assist me to try on your HW.