Re: [PATCH v5 3/9] clk: mediatek: Add configurable pcwibits and fmin to mtk_pll_data
From: Stephen Boyd
Date: Thu Apr 11 2019 - 16:14:44 EST
Quoting Nicolas Boichat (2019-03-07 22:20:27)
> On Tue, Mar 5, 2019 at 1:06 PM Weiyi Lu <weiyi.lu@xxxxxxxxxxxx> wrote:
> > From: Owen Chen <owen.chen@xxxxxxxxxxxx>
> > 1. pcwibits: The integer bits of pcw for plls is extend to 8 bits,
> > add a variable to indicate this change and
> > backward-compatible.
> > 2. fmin: The pll freqency lower-bound is vary from 1GMhz to
> Minor nit: frequency (Stephen I guess you could fix that when applying...)
What's a 1GMhz? Anyway, fixed the typo.