Re: [PATCH v3 0/3] clk: add driver for the SiFive FU540 PRCI and PLLs it controls

[Stephen Boyd]

Quoting Paul Walmsley (2019-04-11 01:26:16)
> clk: add driver for the SiFive FU540 PRCI and PLLs it controls
> 
> Add a driver for the SiFive FU540 PRCI IP block, which handles clock and
> some device reset control for the SiFive FU540 chip.  Also add a driver-
> independent library for the Analog Bits Wide-Range PLL (WRPLL), used by
> the PRCI driver to monitor and control the WRPLL instances on the FU540
> chip.
> 
> Boot-tested on a SiFive HiFive Unleashed board, using BBL and the
> open-source FSBL with a mainline-focused DTB.
> 
> This third version incorporates changes requested by Stephen Boyd
> <sboyd@xxxxxxxxxx> and Rob Herring <robh@xxxxxxxxxx>.
> 
> This patch series is also available, along with the DT macro prerequisite
> patch, at:

Can you please send the dt macro patch along with the rest of the
patches? I can't apply these patches and build them without it.
Typically the macro patch is part of the binding patch and Rob
acks/reviews it as one change. Then I pick that up and the clk driver
parts and they get pulled into whatever SoC tree is using the bindings
header with and those defines get merged up through some other path..

> 
> https://github.com/sifive/riscv-linux/tree/dev/paulw/prci-v5.1-rc4
> 

I suppose I'll go and fetch it from here manually.