Re: [PATCH v2] MIPS: Fix Ingenic SoCs sometimes reporting wrong ISA

From: Paul Burton
Date: Thu May 09 2019 - 19:54:12 EST


Paul Cercueil wrote:
> The config0 register in the Xburst CPUs with a processor ID of
> PRID_COMP_INGENIC_D0 report themselves as MIPS32r2 compatible,
> but they don't actually support this ISA.
> Signed-off-by: Paul Cercueil <paul@xxxxxxxxxxxxxxx>

Applied to mips-next.


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