Re: [PATCH] nvme-pci: Use non-operational power state instead of D3 on Suspend-to-Idle

From: Kai Heng Feng
Date: Fri May 10 2019 - 11:19:52 EST

> On May 10, 2019, at 10:02 PM, Keith Busch <kbusch@xxxxxxxxxx> wrote:
> On Thu, May 09, 2019 at 11:05:42PM -0700, Kai-Heng Feng wrote:
>> Yes, thatâ what I was told by the NVMe vendor, so all I know is to impose a
>> memory barrier.
>> If mb() shouldnât be used here, whatâs the correct variant to use in this
>> context?
> I'm afraid the requirement is still not clear to me. AFAIK, all our
> barriers routines ensure data is visible either between CPUs, or between
> CPU and devices. The CPU never accesses HMB memory, so there must be some
> other reasoning if this barrier is a real requirement for this device.

Sure, Iâll ask vendor what that MemRd is for.