[RFC PATCH] irqchip/gic-v3: Correct the usage of GICD_CTLR's RWP field
From: Zenghui Yu
Date: Mon May 13 2019 - 00:22:29 EST
As per ARM IHI 0069D, GICD_CTLR's RWP field tracks updates to:
GICD_CTLR's Group Enable bits, for transitions from 1 to 0 only
GICD_CTLR's ARE bits, E1NWF bit and DS bit (if we have)
We seemed use this field in an inappropriate way, somewhere in the
GIC-v3 driver. For some examples:
In gic_set_affinity(), if the interrupt was not enabled, we only need
to write GICD_IROUTER<n> with the appropriate mpidr value. Updates to
GICD_IROUTER will not be tracked by RWP field, and we can remove the
unnecessary RWP waiting.
In gic_dist_init(), we "Enable distributor with ARE, Group1" by writing
to GICD_CTLR, and we should use gic_dist_wait_for_rwp() here.
These two are obvious cases, and there are some other cases where we don't
need to do RWP waiting, such as in gic_configure_irq() and gic_poke_irq().
But too many modifications makes me not confident. It's hard for me to say
whether this patch is doing the right thing and how does the RWP waiting
affect the system, thus RFC.
Signed-off-by: Zenghui Yu <yuzenghui@xxxxxxxxxx>
drivers/irqchip/irq-gic-v3.c | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index 15e55d3..8d63950 100644
@@ -600,6 +600,7 @@ static void __init gic_dist_init(void)
/* Enable distributor with ARE, Group1 */
writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1,
base + GICD_CTLR);
* Set all global interrupts to the boot CPU only. ARE must be
@@ -986,14 +987,9 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
- * If the interrupt was enabled, enabled it again. Otherwise,
- * just wait for the distributor to have digested our changes.
+ /* If the interrupt was enabled, enabled it again. */