Re: [PATCH 2/3] mmc: meson-gx: add ddr-access-quirk

From: Kevin Hilman
Date: Mon May 13 2019 - 13:49:24 EST

Neil Armstrong <narmstrong@xxxxxxxxxxxx> writes:

> On the Amlogic G12A SoC family, (only) the SDIO controller fails to access
> the data from DDR, leading to a broken controller.
> But each MMC controller has 1,5KiB of SRAM after the registers, that can
> be used as bounce buffer to avoid direct DDR access from the integrated
> DMAs (this SRAM may be used by the boot ROM when DDR is not yet initialized).
> The quirk is to disable the chained descriptor for this controller, and
> use this SRAM memory zone as buffer for the bounce buffer fallback mode.
> The performance hit hasn't been evaluated, but the fix has been tested
> using a WiFi AP6398S SDIO module, and the iperf3 Bandwidth measurement gave
> 55.2 Mbits/sec over a 63 Hours long test, with the SDIO ios set as High-Speed
> at 50MHz clock. It gave 170 Mbits/sec as SDR104 and 200MHz clock.
> Signed-off-by: Neil Armstrong <narmstrong@xxxxxxxxxxxx>

Reviewed-by: Kevin Hilman <khilman@xxxxxxxxxxxx>