[v2, PATCH 4/4] net: stmmac: dwmac-mediatek: modify csr_clk value to fix mdio read/write fail

From: Biao Huang
Date: Mon May 13 2019 - 22:30:59 EST


1. the frequency of csr clock is 66.5MHz, so the csr_clk value should
be 0 other than 5.
2. the csr_clk can be got from device tree, so remove initialization here.

Change-Id: I3cd92fe380150fec6daa2d3acaab69a6d58344c0
Signed-off-by: Biao Huang <biao.huang@xxxxxxxxxxxx>
---
.../net/ethernet/stmicro/stmmac/dwmac-mediatek.c | 2 --
1 file changed, 2 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c
index bf25629..126b66b 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c
@@ -346,8 +346,6 @@ static int mediatek_dwmac_probe(struct platform_device *pdev)
return PTR_ERR(plat_dat);

plat_dat->interface = priv_plat->phy_mode;
- /* clk_csr_i = 250-300MHz & MDC = clk_csr_i/124 */
- plat_dat->clk_csr = 5;
plat_dat->has_gmac4 = 1;
plat_dat->has_gmac = 0;
plat_dat->pmt = 0;
--
1.7.9.5