Re: [PATCH v7 00/13] selftests/resctrl: Add resctrl selftest
From: James Morse
Date: Tue May 14 2019 - 13:22:01 EST
On 10/05/2019 20:20, Yu, Fenghua wrote:
>> On Friday, May 10, 2019 10:36 AM
>> Andre Przywara [mailto:andre.przywara@xxxxxxx] wrote:
>> On Sat, 9 Feb 2019 18:50:29 -0800
>> Fenghua Yu <fenghua.yu@xxxxxxxxx> wrote:
>>> With more and more resctrl features are being added by Intel, AMD and
>>> ARM, a test tool is becoming more and more useful to validate that
>>> both hardware and software functionalities work as expected.
>> That's very much appreciated! We decided to use that tool here to detect
>> regressions in James' upcoming resctrl rework series. While doing so we
>> spotted some shortcomings:
>> - There is some unconditional x86 inline assembly which obviously breaks
>> the build on ARM.
> Will fix this as much as possible.
> BTW, does ARM support perf imc_count events which are used in CAT tests?
I've never heard of these. git-grep says its a powerpc pmu...
(after a quick chat with Andre), is this a cache-miss counter?
If so, its a bit murky, (and beware, I don't know much about perf).
The arch code's armv8_pmu has a 'PERF_COUNT_HW_CACHE_MISSES' map entry, so yes...
... but if we're measuring this on a cache outside the CPU, we'd need an 'uncore' pmu
driver, so it would depend on what the manufacturer implemented.
I should admit that I'm expecting this selftest to test resctrl, and not depend on a lot
else. Couldn't it use the llc_occupancy value, 50% bitmap gives ~50% lower occupancy. Or
(some combination of) the mbm byte counters, (which would require a seeky workload to
cause repeat re-fills of the same line)...