Re: [PATCH V7 05/15] PCI: dwc: Add ext config space capability search API

[Vidya Sagar]

On 5/21/2019 4:06 PM, Thierry Reding wrote:
> On Fri, May 17, 2019 at 06:08:36PM +0530, Vidya Sagar wrote:
> > Add extended configuration space capability search API using struct dw_pcie *
> > pointer
> >
> > Signed-off-by: Vidya Sagar <vidyas@xxxxxxxxxx>
> > Acked-by: Gustavo Pimentel <gustavo.pimentel@xxxxxxxxxxxx>
> > ---
> > Changes since [v6]:
> > * None
> >
> > Changes since [v5]:
> > * None
> >
> > Changes since [v4]:
> > * None
> >
> > Changes since [v3]:
> > * None
> >
> > Changes since [v2]:
> > * None
> >
> > Changes since [v1]:
> > * This is a new patch in v2 series
> >
> >   drivers/pci/controller/dwc/pcie-designware.c | 41 ++++++++++++++++++++
> >   drivers/pci/controller/dwc/pcie-designware.h |  1 +
> >   2 files changed, 42 insertions(+)
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> > index 8f53ce63d17e..3b7d50888caa 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware.c
> > +++ b/drivers/pci/controller/dwc/pcie-designware.c
> > @@ -54,6 +54,47 @@ u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap)
> >   }
> >   EXPORT_SYMBOL_GPL(dw_pcie_find_capability);
> >   
> > +static int dw_pcie_find_next_ext_capability(struct dw_pcie *pci, int start,
> > +					    int cap)
>
> Perhaps make this more consistent with the existing regular
> configuration space capability search API? Something like this perhaps:
>
> 	static u16 dw_pcie_find_next_ext_capability(struct dw_pcie *pci,
> 						    u16 start, u8 cap)
>
> ? I guess your variant above is consistent with the existing generic
> capability search API, so another alternative might be to make the old
> dw_pcie_find_capability() API consistent with everything else. It's
> confusing if we keep having to jump between the two variants.
Ok. I'll change it to the format being followed in this file i.e. using u16 and u8

> Thierry
>
> > +{
> > +	u32 header;
> > +	int ttl;
> > +	int pos = PCI_CFG_SPACE_SIZE;
> > +
> > +	/* minimum 8 bytes per capability */
> > +	ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
> > +
> > +	if (start)
> > +		pos = start;
> > +
> > +	header = dw_pcie_readl_dbi(pci, pos);
> > +	/*
> > +	 * If we have no capabilities, this is indicated by cap ID,
> > +	 * cap version and next pointer all being 0.
> > +	 */
> > +	if (header == 0)
> > +		return 0;
> > +
> > +	while (ttl-- > 0) {
> > +		if (PCI_EXT_CAP_ID(header) == cap && pos != start)
> > +			return pos;
> > +
> > +		pos = PCI_EXT_CAP_NEXT(header);
> > +		if (pos < PCI_CFG_SPACE_SIZE)
> > +			break;
> > +
> > +		header = dw_pcie_readl_dbi(pci, pos);
> > +	}
> > +
> > +	return 0;
> > +}
> > +
> > +int dw_pcie_find_ext_capability(struct dw_pcie *pci, int cap)
> > +{
> > +	return dw_pcie_find_next_ext_capability(pci, 0, cap);
> > +}
> > +EXPORT_SYMBOL_GPL(dw_pcie_find_ext_capability);
> > +
> >   int dw_pcie_read(void __iomem *addr, int size, u32 *val)
> >   {
> >   	if (!IS_ALIGNED((uintptr_t)addr, size)) {
> > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> > index 6cb978132469..fff284098117 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware.h
> > +++ b/drivers/pci/controller/dwc/pcie-designware.h
> > @@ -252,6 +252,7 @@ struct dw_pcie {
> >   		container_of((endpoint), struct dw_pcie, ep)
> >   
> >   u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap);
> > +int dw_pcie_find_ext_capability(struct dw_pcie *pci, int cap);
> >   
> >   int dw_pcie_read(void __iomem *addr, int size, u32 *val);
> >   int dw_pcie_write(void __iomem *addr, int size, u32 val);
> > --
> > 2.17.1