[PATCH v3 01/12] dt-bindings: media: sunxi-ir: add A31 compatible

From: ClÃment PÃron
Date: Tue May 28 2019 - 12:18:23 EST

Allwinner A31 has introduced a new memory mapping and a
reset line.

The difference in memory mapping are :

- In the configure register there is a new sample bit
and Allwinner has introduced the active threshold feature.

- In the status register a new STAT bit is present.

Note: CGPO and DRQ_EN bits are removed on A31 but present on A13
and on new SoCs like A64/H6.
This is actually not an issue as these bits are togglable and new
SoCs have a dedicated bindings.

Introduce this bindings to make a difference since this generation.
And declare the reset line required since A31.

Signed-off-by: ClÃment PÃron <peron.clem@xxxxxxxxx>
Documentation/devicetree/bindings/media/sunxi-ir.txt | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/media/sunxi-ir.txt b/Documentation/devicetree/bindings/media/sunxi-ir.txt
index 278098987edb..2e59a32a7e33 100644
--- a/Documentation/devicetree/bindings/media/sunxi-ir.txt
+++ b/Documentation/devicetree/bindings/media/sunxi-ir.txt
@@ -1,16 +1,21 @@
Device-Tree bindings for SUNXI IR controller found in sunXi SoC family

Required properties:
-- compatible : "allwinner,sun4i-a10-ir" or "allwinner,sun5i-a13-ir"
+- compatible :
+ "allwinner,sun4i-a10-ir"
+ "allwinner,sun5i-a13-ir"
+ "allwinner,sun6i-a31-ir"
- clocks : list of clock specifiers, corresponding to
entries in clock-names property;
- clock-names : should contain "apb" and "ir" entries;
- interrupts : should contain IR IRQ number;
- reg : should contain IO map address for IR.

+Required properties since A31:
+- resets : phandle + reset specifier pair
Optional properties:
- linux,rc-map-name: see rc.txt file in the same directory.
-- resets : phandle + reset specifier pair
- clock-frequency : IR Receiver clock frequency, in Hertz. Defaults to 8 MHz
if missing.