Re: [PATCH 2/9] perf/x86/intel: Basic support for metrics counters

[Liang, Kan]

On 5/29/2019 3:28 AM, Peter Zijlstra wrote:
> On Tue, May 28, 2019 at 02:21:49PM -0400, Liang, Kan wrote:
> > On 5/28/2019 8:15 AM, Peter Zijlstra wrote:
> > > On Tue, May 21, 2019 at 02:40:48PM -0700, kan.liang@xxxxxxxxxxxxxxx wrote:
> > > > +/*
> > > > + * We model PERF_METRICS as more magic fixed-mode PMCs, one for each metric
> > > > + * and another for the whole slots counter
> > > > + *
> > > > + * Internally they all map to Fixed Ctr 3 (SLOTS), and allocate PERF_METRICS
> > > > + * as an extra_reg. PERF_METRICS has no own configuration, but we fill in
> > > > + * the configuration of FxCtr3 to enforce that all the shared users of SLOTS
> > > > + * have the same configuration.
> > > > + */
> > > > +#define INTEL_PMC_IDX_FIXED_METRIC_BASE		(INTEL_PMC_IDX_FIXED + 17)
> > > > +#define INTEL_PMC_IDX_TD_RETIRING		(INTEL_PMC_IDX_FIXED_METRIC_BASE + 0)
> > > > +#define INTEL_PMC_IDX_TD_BAD_SPEC		(INTEL_PMC_IDX_FIXED_METRIC_BASE + 1)
> > > > +#define INTEL_PMC_IDX_TD_FE_BOUND		(INTEL_PMC_IDX_FIXED_METRIC_BASE + 2)
> > > > +#define INTEL_PMC_IDX_TD_BE_BOUND		(INTEL_PMC_IDX_FIXED_METRIC_BASE + 3)
> > > > +#define INTEL_PMC_MSK_ANY_SLOTS			((0xfull << INTEL_PMC_IDX_FIXED_METRIC_BASE) | \
> > > > +						 INTEL_PMC_MSK_FIXED_SLOTS)
> > > > +static inline bool is_metric_idx(int idx)
> > > > +{
> > > > +	return idx >= INTEL_PMC_IDX_FIXED_METRIC_BASE && idx <= INTEL_PMC_IDX_TD_BE_BOUND;
> > > > +}
> > >
> > > Something like:
> > >
> > > 	return (idx >> INTEL_PMC_IDX_FIXED_METRIC_BASE) & 0xf;
> > >
> > > might be faster code... (if it wasn't for 64bit literals being a pain,
> > > it could be a simple test instruction).
> >
> > is_metric_idx() is not a mask. It's to check if the idx between 49 and 52.
>
> blergh, indeed. Check that it compiles into a single branch though, if
> it gets that wrong it needs hand holding.
>
> One way would be to make these 48-51 and put BTS as 52, and then you do

Can we put BTS 47?
Now we only support L1 Topdown metrics. Probably there will be L2 
Topdown metrics. I think we need some space to extend.


Thanks,
Kan

> have a mask.
>
> Another way would be to write it as:
>
> 	(unsigned)(idx - INTEL_PMC_IDX_FIXED_METRIC_BASE) < 4;