Re: [PATCH v3 4/5] riscv: dts: add initial support for the SiFive FU540-C000 SoC

From: Loys Ollivier
Date: Tue Jun 04 2019 - 10:42:52 EST

On Sun 02 Jun 2019 at 01:04, Paul Walmsley <paul.walmsley@xxxxxxxxxx> wrote:

> Add initial support for the SiFive FU540-C000 SoC. This is a 28nm SoC
> based around the SiFive U54-MC core complex and a TileLink
> interconnect.
> This file is expected to grow as more device drivers are added to the
> kernel.
> This patch includes a fix to the QSPI memory map due to a
> documentation bug, found by ShihPo Hung <shihpo.hung@xxxxxxxxxx>, adds
> entries for the I2C controller, and merges all DT changes that
> formerly were made dynamically by the riscv-pk BBL proxy kernel.
> Signed-off-by: Paul Walmsley <paul.walmsley@xxxxxxxxxx>
> Signed-off-by: Paul Walmsley <paul@xxxxxxxxx>
Tested-by: Loys Ollivier <lollivier@xxxxxxxxxxxx>
> Cc: Rob Herring <robh+dt@xxxxxxxxxx>
> Cc: Mark Rutland <mark.rutland@xxxxxxx>
> Cc: Palmer Dabbelt <palmer@xxxxxxxxxx>
> Cc: Albert Ou <aou@xxxxxxxxxxxxxxxxx>
> Cc: ShihPo Hung <shihpo.hung@xxxxxxxxxx>
> Cc: devicetree@xxxxxxxxxxxxxxx
> Cc: linux-riscv@xxxxxxxxxxxxxxxxxxx
> Cc: linux-kernel@xxxxxxxxxxxxxxx