On 06-05-19, 18:34, Sameer Pujar wrote:I discussed this internally with HW folks and below is the reason why DMA needs
On 5/4/2019 3:53 PM, Vinod Koul wrote:right and people use burst size for precisely that!
On 02-05-19, 18:59, Sameer Pujar wrote:I am using DMA HW in cyclic mode for data transfers to Audio sub-system.
On 5/2/2019 5:55 PM, Vinod Koul wrote:I still do not comprehend why dma would care about slave side
On 02-05-19, 16:23, Sameer Pujar wrote:Yes, I mentioned about FIFO length.
On 5/2/2019 11:34 AM, Vinod Koul wrote:Are you sure, have you talked to HW folks on that? IIUC you are
On 30-04-19, 17:00, Sameer Pujar wrote:Yes, FIFO size is a HW property. But it is SW configurable(atleast in my
During the DMA transfers from memory to I/O, it was observed that transfersFIFO size is a hardware property not sure why you would want an
were inconsistent and resulted in glitches for audio playback. It happened
because fifo size on DMA did not match with slave channel configuration.
currently 'dma_slave_config' structure does not have a field for fifo size.
Hence the platform pcm driver cannot pass the fifo size as a slave_config.
Note that 'snd_dmaengine_dai_dma_data' structure has fifo_size field which
cannot be used to pass the size info. This patch introduces fifo_size field
and the same can be populated on slave side. Users can set required size
for slave peripheral (multiple channels can be independently running with
different fifo sizes) and the corresponding sizes are programmed through
dma_slave_config on DMA side.
interface to program that?
On mismatch, I guess you need to take care of src/dst_maxburst..
slave side and can be set to different sizes. The src/dst_maxburst is
programming the data to be used in FIFO not the FIFO length!
1. MAX FIFO size is fixed in HW. But there is a way to limit the usage per
ÂÂ in multiples of 64 bytes.
2. Having a separate member would give independent control over MAX BURST
ÂÂ FIFO SIZE.
I am not sure if there is any HW logic that mandates DMA to know the sizeprogrammedPrecisely
for specific values, I think this depends on few factors related to
needs of client, DMA needs of the system etc.,
In such cases how does DMA know the actual FIFO depth of slave peripheral?Why should DMA know? Its job is to push/pull data as configured by
peripheral driver. The peripheral driver knows and configures DMA
of configured FIFO depth on slave side. I will speak to HW folks and
would update here.
configuration. In the absence of patch which uses this I am not sure
what you are trying to do...
In such cases flow control on DMA transfers is essential, since I/O is
consuming/producing the data at slower rate. The DMA tranfer is enabled/not really, knowing that doesnt help anyway you have described! DMA
disabled during start/stop of audio playback/capture sessions through ALSA
callbacks and DMA runs in cyclic mode. Hence DMA is the one which is doing
flow control and it is necessary for it to know the peripheral FIFO depth
to avoid overruns/underruns.
pushes/pulls data and that is controlled by burst configured by slave
(so it know what to expect and porgrams things accordingly)
you are really going other way around about the whole picture. FWIW that
is how *other* folks do audio with dmaengine!
Also please note that, peripheral device has multiple channels and shareyeah peripheral driver, yes. DMA driver nope!
a fixed MAX FIFO buffer. But SW can program different FIFO sizes for