Re: [RFC PATCH] x86/cpufeatures: Enumerate new AVX512 bfloat16 instructions
From: Fenghua Yu
Date: Tue Jun 11 2019 - 14:33:14 EST
On Mon, Jun 10, 2019 at 09:20:26PM +0200, Borislav Petkov wrote:
> On Mon, Jun 10, 2019 at 10:02:38AM -0700, Fenghua Yu wrote:
> > AVX512 Vector Neural Network Instructions (VNNI) in Intel Deep Learning
> > Boost support bfloat16 format (BF16). BF16 is a short version of FP32 and
> > has several advantages over FP16. BF16 offers more than enough range for
> > deep learning training tasks and doesn't need to handle hardware exception
> > as this is a performance optimization. FP32 accumulation after the
> > multiply is essential to achieve sufficient numerical behavior on an
> > application level.
> > AVX512 bfloat16 instructions can be enumerated by:
> > CPUID.(EAX=7,ECX=1):EAX[bit 5] AVX512_BF16
> > Detailed information of the CPUID bit and AVX512 bfloat16 instructions
> > can be found in the latest Intel Architecture Instruction Set Extensions
> > and Future Features Programming Reference.
> > Signed-off-by: Fenghua Yu <fenghua.yu@xxxxxxxxx>
> > ---
> > Since split lock feature (to-be-upstreamed) occupies the last bit
> > of word 7, need to create a new word 19 to host AVX512_BF16 and other
> > future features.
> Is CPUID.(EAX=7,ECX=1):EAX going to contain only feature bits? If so,
> just make it a proper feature word instead of a linux-specific one.
AFAICT, there will be more features in the EAX register in the future.
Ok. I will use a feature word for CPUID.(EAX=7,ECX=1):EAX.
> Also, while on the subject, you can recycle word 11
> /* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:0 (EDX), word 11 */
> #define X86_FEATURE_CQM_LLC (11*32+ 1) /* LLC QoS if 1 */
> and move it to scattered as it is a complete waste. Word 12 too, for
> that matter. But do that in separate patches.
So can I re-organize word 11 and 12 as follows?
1. Change word 11 to host scattered features.
2. Move the previos features in word 11 and word 12 to word 11:
* Extended auxiliary flags: Linux defined - For features scattered in various
* CPUID levels and sub-leaves like CPUID level 7 and sub-leaf 1, etc, word 19.
#define X86_FEATURE_CQM_LLC (11*32+ 0) /* LLC QoS if 1 */
#define X86_FEATURE_CQM_OCCUP_LLC (11*32+ 1) /* LLC occupancy monitoring */
#define X86_FEATURE_CQM_MBM_TOTAL (11*32+ 2) /* LLC Total MBM monitoring */
#define X86_FEATURE_CQM_MBM_LOCAL (11*32+ 3) /* LLC Local MBM monitoring */
3. Change word 12 to host CPUID.(EAX=7,ECX=1):EAX:
/* Intel-defined CPU features, CPUID level 0x7:1 (EAX), word 12 */
#define X86_FEATURE_AVX512_BF16 (12*32+ 0) /* BFLOAT16 instructions */
4. Do other necessary changes to match the new word 11 and word 12.