On 06-06-19, 09:19, Sameer Pujar wrote:Signal is triggered when FIFO read/write happens on the peripheral side. In other words
when is signal triggered? When there is space available or someyou are really going other way around about the whole picture. FWIW thatI discussed this internally with HW folks and below is the reason why DMA
is how *other* folks do audio with dmaengine!
to know FIFO size.
- FIFOs reside in peripheral device(ADMAIF), which is the ADMA interface to
the audio sub-system.
- ADMAIF has multiple channels and share FIFO buffer for individual
operations. There is a provision
Â to allocate specific fifo size for each individual ADMAIF channel from the
- Tegra Audio DMA(ADMA) architecture is different from the usual DMA
engines, which you described earlier.
- The flow control logic is placed inside ADMA. Slave peripheral
device(ADMAIF) signals ADMA whenever a
Â read or write happens on the FIFO(per WORD basis). Please note that the
signaling is per channel. There is
Â no other signaling present from ADMAIF to ADMA.
- ADMA keeps a counter related to above signaling. Whenever a sufficient
threshold of space is reached?
No, In our case ADMAIF does not do any threshold based signalling to ADMA.space is available, it initiates a transfer.That doesn't sound too different from typical dmaengine. To give an
Â But the question is, how does it know when to transfer. This is the
reason, why ADMA has to be aware of FIFO
Â depth of ADMAIF channel. Depending on the counters and FIFO depth, it
knows exactly when a free space is available
Â in the context of a specific channel. On ADMA, FIFO_SIZE is just a value
which should match to actual FIFO_DEPTH/SIZE
Â of ADMAIF channel.
example of a platform (and general DMAengine principles as well) I worked
on the FIFO was 16 word deep. DMA didn't knew!
Peripheral driver would signal to DMA when a threshold is reached and
DMA would send a burst controlled by src/dst_burst_size. For example ifThe scenario is different in ADMA case, as ADMAIF cannot configure the
you have a FIFO with 16 words depth, typical burst_size would be 8 words
and peripheral will configure signalling for FIFO having 8 words, so
signal from peripheral will make dma transfer 8 words.
Say for example FIFO_THRESHOLD is programmed as 16 WORDS, BURST_SIZE as 8 WORDS.
Here the peripheral driver FIFO is important, but the driver
configures it and sets burst_size accordingly.
So can you explain me what is the difference here that the peripheral
cannot configure and use burst size with passing fifo depth?
- Now consider two cases based on above logic,
Â * Case 1: when DMA_FIFO_SIZE > SLAVE_FIFO_SIZE
ÂÂÂ In this case, ADMA thinks that there is enough space available for
transfer, when actually the FIFO data
ÂÂÂ on slave is not consumed yet. It would result in OVERRUN.
Â * Case 2: when DMA_FIFO_SIZE < SLAVE_FIFO_SIZE
ÂÂÂ This is case where ADMA wonât transfer, even though sufficient space is
available, resulting in UNDERRUN.
- The guideline is to program, DMA_FIFO_SIZE(on ADMA side) =
SLAVE_FIFO_SIZE(on ADMAIF side) and hence we need a
Â way to communicate fifo size info to ADMA.