Re: [PATCH v1 23/50] ARM: dts: exynos: change lowest OPP in bus_disp1_fimd in Exynos5420
From: Krzysztof Kozlowski
Date: Wed Jul 17 2019 - 05:08:28 EST
On Mon, 15 Jul 2019 at 14:44, Lukasz Luba <l.luba@xxxxxxxxxxxxxxxxxxx> wrote:
> The lowest OPP must be aligned to possible value after division of parent
> clock rate. Thus, change it to the value which is true for clock 1200MHz.
I think this is getting slightly too granular. It seems you are
solving the same problem (or very small subset of the same problem) as
in patch 22:
Please combine such changes per IP block, unless you have really
reproducible different issues (e.g. reproducible different performance
problem or OOPS, but not just what clk_summary prints). I imagine that
you align entire subsystem (DISP) buses to real clock frequencies (or
to match real frequencies, or to achieve more granular scaling, or to
get slightly better performance).