Re: [PATCH V5 11/18] clk: tegra210: Add support for Tegra210 clocks

From: Sowjanya Komatineni
Date: Thu Jul 18 2019 - 13:22:31 EST

On 7/18/19 9:34 AM, Dmitry Osipenko wrote:
18.07.2019 4:15, Sowjanya Komatineni ÐÐÑÐÑ:


Please try to fix all missing dependencies and orderings.

dfllCPU_OUT is the first one to go thru restore when
clk_restore_context traverses thru the list.

dfllCPU_OUT has dependency on DFLL_ref and DFLL_SOC but this
dependency is unknown to clock-tree.

We can add DFLL_REF and DFLL_SOC as parents to dfllCPU_OUT during
register so dfllCPU_OUT save/restore happens after their parents are

But DFLL needs both of these to be restored before DFLLCPU_Out and as
DFLL_SOC restore always happens after the REF, thinking to add
DFLL_SOC as parent to dfllCPU_OUT so save/restore follows after their

Please comment.

Did quick try and I see by adding dfll-soc as parent to dfllCPU_OUT, its
in proper order after all its dependencies.

Can now add dfll save/restore to do dfll reinit during restore..

If dfllCPU_OUT can work properly with dfll-soc being disabled, then this
kind of dependency isn't very correct and just papers over the real
problem, which is that there should be a way for CCF to specify multiple
dependencies for the clock or the reverse ordering should be used for
the restoring.

dfll will not work without dfll-soc enabled.

CLDVFS control logic is split into 2 clock domains. dvfs_ref_clk and dvfs_soc_clk.

Majority of the control logic is clocked from dvfs_soc_clk for interfacing control registers.