Re: [PATCH] perf/x86/amd: Change NMI latency mitigation to use a timestamp
From: Peter Zijlstra
Date: Fri Aug 02 2019 - 12:20:27 EST
On Fri, Aug 02, 2019 at 02:33:41PM +0000, Lendacky, Thomas wrote:
> On 8/1/19 4:59 PM, Thomas Gleixner wrote:
> > On Thu, 1 Aug 2019, Peter Zijlstra wrote:
> >> On Thu, Aug 01, 2019 at 11:34:23PM +0200, Thomas Gleixner wrote:
> >>> Avoid the whole NMI mess, make the PMC interrupt a proper vector in the
> >>> highest prio bucket and instead of using CLI/STI use CR8. That would have
> >>> the additional advantage that we could prevent perf "NMI" then occsionally :)
> >> Exactly, and not only the PMC, we can basically start giving out actual
> >> vectors on register_nmi_handler() and do away with all that shared line
> >> crap.
> >> And then the actual NMI line will be mostly empty again, and it can read
> >> its stupid slow reason port again.
> >> One complication though; IRET et al only do EFLAGS, not CR8, so that's
> >> going to be massive fun :-(
> Talking to the hardware folks, they say setting CR8 is a serializing
> instruction and has to communicate out to the APIC, so it's better to
> use CLI/STI.
Bah; the Intel SDM states: "MOV CR* instructions, except for MOV CR8,
are serializing instructions", which had given me a little hope.
At the same time, all these chips still have the APIC TPR field too, so
much like how the TSC DEADLINE MSR is a hidden APIC write, so too is CR8
I suppose :-(
I'll still finish the patches I started, just to see what it would look
Thomas mentioned combining this with software IRQ disable (like Power),
but at that point maybe full software priorities aren't too bad either.