RE: [PATCH 1/4] dt-bingings: PCI: Remove the num-lanes from Required properties
From: Z.q. Hou
Date: Mon Aug 12 2019 - 23:07:29 EST
Thanks a lot for your comments!
> -----Original Message-----
> From: Andrew Murray <andrew.murray@xxxxxxx>
> Sent: 2019年8月12日 16:45
> To: Z.q. Hou <zhiqiang.hou@xxxxxxx>
> Cc: linux-pci@xxxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx;
> linux-kernel@xxxxxxxxxxxxxxx; gustavo.pimentel@xxxxxxxxxxxx;
> jingoohan1@xxxxxxxxx; bhelgaas@xxxxxxxxxx; robh+dt@xxxxxxxxxx;
> mark.rutland@xxxxxxx; shawnguo@xxxxxxxxxx; Leo Li
> <leoyang.li@xxxxxxx>; lorenzo.pieralisi@xxxxxxx; M.h. Lian
> <minghuan.lian@xxxxxxx>; Kishon Vijay Abraham I <kishon@xxxxxx>;
> Gabriele Paoloni <gabriele.paoloni@xxxxxxxxxx>
> Subject: Re: [PATCH 1/4] dt-bingings: PCI: Remove the num-lanes from
> Required properties
> On Mon, Aug 12, 2019 at 04:22:16AM +0000, Z.q. Hou wrote:
> > From: Hou Zhiqiang <Zhiqiang.Hou@xxxxxxx>
> > The num-lanes is not a mandatory property, e.g. on FSL Layerscape
> > SoCs, the PCIe link training is completed automatically base on the
> > selected SerDes protocol, it doesn't need the num-lanes to set-up the
> > link width.
> > It has been added in the Optional properties. This patch is to remove
> > it from the Required properties.
> For clarity, maybe this paragraph can be reworded to:
> "It is previously in both Required and Optional properties, let's remove it
> from the Required properties".
Agree and will change in v2.
> I don't understand why this property is previously in both required and
> It looks like num-lanes was first made optional back in
> 2015 and removed from the Required section (907fce090253).
> But then re-added back into the Required section in 2017 with the adition of
> bindings for EP mode (b12befecd7de).
> Is num-lanes actually required for EP mode?
Kishon, please help to answer this query?
> Andrew Murray
> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@xxxxxxx>
> > ---
> > Documentation/devicetree/bindings/pci/designware-pcie.txt | 1 -
> > 1 file changed, 1 deletion(-)
> > diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt
> > b/Documentation/devicetree/bindings/pci/designware-pcie.txt
> > index 5561a1c060d0..bd880df39a79 100644
> > --- a/Documentation/devicetree/bindings/pci/designware-pcie.txt
> > +++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt
> > @@ -11,7 +11,6 @@ Required properties:
> > the ATU address space.
> > (The old way of getting the configuration address space from
> > is deprecated and should be avoided.)
> > -- num-lanes: number of lanes to use
> > RC mode:
> > - #address-cells: set to <3>
> > - #size-cells: set to <2>
> > --
> > 2.17.1