Re: [PATCH v2 4/6] dt: bindings: add mt7621-pll dt binding documentation

From: Oleksij Rempel
Date: Sat Aug 17 2019 - 11:40:23 EST


Am 17.08.19 um 16:42 schrieb Chuanhong Guo:

On Tue, Aug 13, 2019 at 11:51 PM Rob Herring <robh@xxxxxxxxxx> wrote:
+ pll {
+ compatible = "mediatek,mt7621-pll";

You didn't answer Stephen's question on v1.

I thought he was asking why there's a syscon in compatible string. I
noticed that the syscon in my previous patch is a copy-paste error
from elsewhere and dropped it.

Based on this binding, there is no way to control/program the PLL. Is
this part of some IP block?

The entire section is called "system control" in datasheet and is
occupied in arch/mips/ralink/mt7621.c [0]
Two clocks provided here is determined by reading some read-only
registers in this part.
There's another register in this section providing clock gates for
every peripherals, but MTK doesn't provide a clock plan in their
datasheet. I can't determine corresponding clock frequencies for every
peripherals, thus unable to write a working clock driver.

In provided link [0] the ralink_clk_init function is reading SYSC_REG_CPLL_CLKCFG0 R/W register.
This register is used to determine clock source, clock freq and CPU or bus clocks.
SYSC_REG_CPLL_CLKCFG1 register is a clock gate controller. It is used to enable or disable clocks.
Jist wild assumption. All peripheral devices are suing bus clock.

IMO - this information is enough to create full blown drivers/clk/mediatek/clk-mt7621.c

+ #clock-cells = <1>;
+ clock-output-names = "cpu", "bus";
+ };

Chuanhong Guo