[PATCHv2 3/4] ARM: dts: ls1021a: Remove num-lanes property from PCIe nodes

[Z.q. Hou]

From: Hou Zhiqiang <Zhiqiang.Hou@xxxxxxx>

Remove the num-lanes to avoid the driver setting the link width.

On FSL Layerscape SoCs, the number of lanes assigned to PCIe
controller is not fixed, it is determined by the selected SerDes
protocol in the RCW (Reset Configuration Word), and the PCIe link
training is completed automatically base on the selected SerDes
protocol, and the link width set-up is updated by hardware after
power on reset. So the num-lanes is not needed for Layerscape PCIe.

The current num-lanes was added erroneously, which actually indicates
the max lanes PCIe controller can support up to, instead of the lanes
assigned to the PCIe controller. And the link width set by SerDes
protocol will be overridden by the num-lanes, hence the subsequent
re-taining will fail when the assigned lanes does not equal to
num-lanes.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@xxxxxxx>
Reviewed-by: Andrew Murray <andrew.murray@xxxxxxx>
---
V2:
 - Reworded the change log.

 arch/arm/boot/dts/ls1021a.dtsi | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 464df4290ffc..2f6977ada447 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -874,7 +874,6 @@
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
-			num-lanes = <4>;
 			num-viewport = <6>;
 			bus-range = <0x0 0xff>;
 			ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
@@ -899,7 +898,6 @@
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
-			num-lanes = <4>;
 			num-viewport = <6>;
 			bus-range = <0x0 0xff>;
 			ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
-- 
2.17.1