Hi guys,Hi Paul,
On Tue, Aug 27, 2019 at 10:18:46PM +0800, Jiaxun Yang wrote:
On 2019/8/27 äå8:45, Rob Herring wrote:In general on MIPS we detect CPU properties at runtime from coprocessor
On Tue, Aug 27, 2019 at 3:55 AM Jiaxun Yang <jiaxun.yang@xxxxxxxxxxx> wrote:Currently it's specific to Loongson CPU only, as other processors may using
diff --git a/Documentation/devicetree/bindings/mips/loongson/cpus.yaml b/Documentation/devicetree/bindings/mips/loongson/cpus.yamlDual license for new bindings please:
new file mode 100644
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: GPL-2.0
(GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2Is this definition specific to Loongson CPUs or all MIPS?
+title: Loongson CPUs bindings
+ - Jiaxun Yang <jiaxun.yang@xxxxxxxxxxx>
+ The device tree allows to describe the layout of CPUs in a system through
+ the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
+ defining properties for every cpu.
+ Bindings for CPU nodes follow the Devicetree Specification, available from:
+ maxItems: 1
+ description: |
+ Physical ID of a CPU, Can be read from CP0 EBase.CPUNum.
different method to express CPU map.
Different from Arm, MIPS family of processors seems less uniform and have
their own designs.
For this point, we'd better ask Paul's opinion.
0 registers & similar sources of information, so there's not really a
need to specify anything about the CPU in devicetree. For example here
you say yourself that the value for this property can be read from
EBase.CPUNum - so why specify it in DT?