Re: [PATCH v2 1/2] dt-bindings: reset: Add YAML schemas for the Intel Reset controller

From: Dilip Kota
Date: Tue Aug 27 2019 - 22:59:51 EST

Hi Rob,

On 8/27/2019 10:04 PM, Dilip Kota wrote:
Hi Rob,

On 8/26/2019 7:23 PM, Rob Herring wrote:
On Mon, Aug 26, 2019 at 4:52 AM Dilip Kota <eswara.kota@xxxxxxxxxxxxxxx> wrote:
Hi Rob,

On 8/23/2019 8:25 PM, Rob Herring wrote:
On Fri, Aug 23, 2019 at 12:28 AM Dilip Kota <eswara.kota@xxxxxxxxxxxxxxx> wrote:
Add YAML schemas for the reset controller on Intel
Lightening Mountain (LGM) SoC.

Signed-off-by: Dilip Kota <eswara.kota@xxxxxxxxxxxxxxx>
Changes on v2:
ÂÂÂÂÂ Address review comments
ÂÂÂÂÂÂÂ Update the compatible property definition
ÂÂÂÂÂÂÂ Add description for reset-cells
ÂÂÂÂÂÂÂ Add 'additionalProperties: false' property

ÂÂ .../bindings/reset/intel,syscon-reset.yamlÂÂÂÂÂÂÂÂ | 53 ++++++++++++++++++++++
ÂÂ 1 file changed, 53 insertions(+)
ÂÂ create mode 100644 Documentation/devicetree/bindings/reset/intel,syscon-reset.yaml

diff --git a/Documentation/devicetree/bindings/reset/intel,syscon-reset.yaml b/Documentation/devicetree/bindings/reset/intel,syscon-reset.yaml
new file mode 100644
index 000000000000..3403a967190a
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/intel,syscon-reset.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+title: Intel Lightening Mountain SoC System Reset Controller
+Â - Dilip Kota <eswara.kota@xxxxxxxxxxxxxxx>
+Â compatible:
+ÂÂÂ items:
+ÂÂÂÂÂ - const: intel,rcu-lgm
+ÂÂÂÂÂ - const: syscon
+Â reg:
+ÂÂÂ description: Reset controller register base address and size
+Â intel,global-reset:
+ÂÂÂ $ref: /schemas/types.yaml#/definitions/uint32-array
+ÂÂÂ description: Global reset register offset and bit offset.
+Â "#reset-cells":
+ÂÂÂ const: 2
+ÂÂÂ description: |
+ÂÂÂÂÂ The 1st cell is the register offset.
+ÂÂÂÂÂ The 2nd cell is the bit offset in the register.
+Â - compatible
+Â - reg
+Â - intel,global-reset
+Â - "#reset-cells"
+additionalProperties: false
+Â - |
+ÂÂÂ rcu0: reset-controller@00000000 {
+ÂÂÂÂÂÂÂ compatible = "intel,rcu-lgm", "syscon";
+ÂÂÂÂÂÂÂ reg = <0x000000 0x80000>;
+ÂÂÂÂÂÂÂ intel,global-reset = <0x10 30>;
+ÂÂÂÂÂÂÂ #reset-cells = <2>;
+ÂÂÂ };
+ÂÂÂ pcie_phy0: pciephy@... {
You need to run 'make dt_binding_check' and fix the warnings. The
example has to be buildable and it is not.
Sure, i will correct this pcie_phy0 node. But i didn't get any warnings
for make dt_binding_check

ÂÂÂ CHKDT Documentation/devicetree/bindings/reset/intel,syscon-reset.yaml
DTC Documentation/devicetree/bindings/arm/renesas.example.dt.yaml
FATAL ERROR: Unknown output format "yaml"

Will DTC report about the example node errors? But, DTC is failing with
I tried it even after installing libyaml and headers in my local
directory and export the path, but no luck.(ref:
Could you please let me know if i miss anything and help me to proceed
See Documentation/devicetree/

I have followed all the steps mentioned in the document before keeping the mail itself.
Does the dtc script looks for libyaml and its header files at any default or specific location?
DTC is working for me now.
It is working for me after updating the libyaml and header paths in scripts/dtc/Makefile and yamltree.c (since i have installed libyaml and header files in my local directories)

I have fixed all the warnings and DTC checks are successful. I will push the changes in the next patch version.
 DTC Documentation/devicetree/bindings/reset/intel,syscon-reset.example.dt.yaml
 CHECK Documentation/devicetree/bindings/reset/intel,syscon-reset.example.dt.yaml