Re: [linux-sunxi] Re: [PATCH] mmc: sunxi: fix unusuable eMMC on some H6 boards by disabling DDR
From: Chen-Yu Tsai
Date: Wed Aug 28 2019 - 09:29:49 EST
On Wed, Aug 28, 2019 at 8:52 PM Linus Walleij <linus.walleij@xxxxxxxxxx> wrote:
> On Sun, Aug 25, 2019 at 5:06 PM Alejandro GonzÃlez
> <alejandro.gonzalez.correo@xxxxxxxxx> wrote:
> > Jernej Skrabec compared the BSP driver with this
> > driver, and found that the BSP driver configures pinctrl to operate at
> > 1.8 V when entering DDR mode (although 3.3 V operation is supported), while
> > the mainline kernel lacks any mechanism to switch voltages dynamically.
AFAIK The Pine H64 does not have the ability to switch I/O voltages. It is
fixed to either 1.8V (the default based on the schematics) or 3.3V.
> > the kernel lacks the required
> > dynamic pinctrl control for now
> This is not a pin control thing, the I/O voltage level is usually
> controlled by a regulator called VCCQ, if the selection of the
> voltage rails is inside the pin control registers, see the solution
> in drivers/pinctrl/sh-pfc/pfc-sh73a0.c where we simply provide
> a regulator from inside the pinctrl driver to make things easy
> for the MMC core. Do this thing!
Or if it's simply voltage trimming for input, the a80 pinctrl driver
has something similar. Basically it registers a notifier on the
voltage rail supplying a set of pins, and toggles the register
to match the external voltage provided.
Unfortunately the user manual is quite vague on what it actually is.
> If you don't have time to fix it up properly right now I would slap
> in a big FIXME in the code so people know this needs
> to be fixed properly.