Hi,For LGM, RCU is clean. There would be no MISC register after software's feedback. These misc registers will be moved to chiptop/misc groups(implemented by syscon). For legacy SoC, we do have a lot MISC registers for different SoCs.
On Thu, Aug 29, 2019 at 4:51 AM Chuan Hua, Lei
OK, just be aware that there are also rules for syscon compatibleI'm not surprised that we got some of the IP block layout for theAs I mentioned, some other misc registers are put into RCU even they
VRX200 RCU "wrong" - all "documentation" we have is the old Lantiq UGW
with proper documentation (as in a "public datasheet for the SoC") it
would be easy to spot these mistakes (at least I assume that the
quality of the Infineon / Lantiq datasheets is excellent).
back to reset-intel-syscon:
assigning only one job to the RCU hardware is a good idea (in my opinion).
that brings up a question: why do we need the "syscon" compatible for
the RCU node?
this is typically used when registers are accessed by another IP block
and the other driver has to access these registers as well. does this
mean that there's more hidden in the RCU registers?
don't belong to reset functions.
drivers, see for example: 
if Rob (dt-bindings maintainer) is happy with the documentation in
patch 1 then I'm fine with it as well.
for my own education I would appreciate if you could describe these
"other misc registers" with a few sentences (I assume that this can
also help Rob)
I see, thank you for the explanationReset status check is there. regmap_read_poll_timeout to check statusonly now I realized that the reset-intel-syscon driver does not seemYes. We have reset pulse(assert, then check the reset status).what about the _reset callback on the XRX350/XRX500/PRX300 SoCs - doOur internal version supports XRX350/XRX500/PRX300(MIPS based) and4. Code not optimized and intel internal review not assessed.insights from you (like the issue with the reset callback) are very
valuable - this shows that we should focus on having one driver.
Based on the above findings, I would suggest reset-lantiq.c to move tomy concern with having two separate drivers is that it will be hard to
migrate from reset-lantiq to the "optimized" reset-intel-syscon
I don't have access to the datasheets for the any Lantiq/Intel SoC
(VRX200 and even older).
so debugging issues after switching from one driver to another is
tedious because I cannot tell which part of the driver is causing a
problem (it's either "all code from driver A" vs "all code from driver
B", meaning it's hard to narrow it down).
with separate commits/patches that are improving the reset-lantiq
driver I can do git bisect to find the cause of a problem on the older
SoCs (VRX200 for example)
latest Lighting Mountain(X86 based). Migration to reset-intel-syscon.c
should be straight forward.
they only use level resets (_assert and _deassert) or are some reset
lines using reset pulses (_reset)?
when we wanted to switch from reset-lantiq.c to reset-intel-syscon.c
we still had to add support for the _reset callback as this is missing
in reset-intel-syscon.c currently
to use the status registers (instead it's looking at the reset
registers when checking the status).
what happened to the status registers - do they still exist in newer
SoCs (like LGM)? why are they not used?
big. Status register offset <4) from request register. For legacy, there
is one exception, we can add soc specific data to handle it.
this won't work on VRX200 for example because the status register is
not always at (reset register - 0x4)
LGM reset organization is more clean compared with legacy SoCs. We have 8 x 32bit reset and status registers(more modules need to be reset, overall ideas are similar without big change). Their request and status bit is at the same register bit position.Â Hope this will help you.
with reset-lantiq we have the following register information:on VRX200 for example there seem to be some cases where the bits inThis is most tricky and ugly part for VRX200/Danube. Do you have any
the reset and status registers are different (for example: the first
GPHY seems to use reset bit 31 but status bit 30)
this is currently not supported in reset-intel-syscon
idea to handle this nicely?
a) reset offset: first reg property
b) status offset: second reg property
c) reset bit: first #reset-cell
d) status bit: second #reset-cell
reset-intel-syscon derives half of this information from the two #reset-cells:
a) reset offset: first #reset-cell
b) status offset: reset offset - 0x4
c) reset bit: second #reset-cell
d) status bit: same as reset bit
I cannot make any suggestion (yet) how to handle VRX200 and LGM in one
driver because I don't know enough about LGM (yet).
on VRX200 my understanding is that we have 64 reset bits (2x 32bit
registers) and 64 status bits (also 2x 32bit registers). each reset
bit has a corresponding status bit but the numbering may be different
it's not clear to me how many resets LGM supports and how they are
organized. for example: I think it makes a difference if "there are 64
registers with each one reset bit" versus "there are two registers
with 32 bits each"
please share some details how it's organized internally, then I can
try to come up with a suggestion.
... after writing this I noticed that we are discussing the binding.
we definitely need to share a summary with Rob on patch #1 and check
with him if he sees any problems with the approach that we may come up