Re: mtd raw nand denali.c broken for Intel/Altera Cyclone V
From: Masahiro Yamada
Date: Tue Sep 10 2019 - 03:17:29 EST
On Fri, Sep 6, 2019 at 9:39 PM Tim Sander <tim@xxxxxxxxxxxxxxx> wrote:
> I have noticed that there multiple breakages piling up for the denali nand
> driver on the Intel/Altera Cyclone V. Unfortunately i had no time to track the
> mainline kernel closely. So the breakage seems to pile up. I am a little
> disapointed that Intel is not on the lookout that the kernel works on the
> chips they are selling. I was really happy about the state of the platform
> before concerning mainline support.
> The failure starts with kernel 4.19 or stable kernel release 4.18.19. The
> commit is ba4a1b62a2d742df9e9c607ac53b3bf33496508f.
Just for clarification, this corresponds to
> The problem here is that
> our platform works with a zero in the SPARE_AREA_SKIP_BYTES register.
Please clarify the scope of "our platform".
(Only you, or your company, or every individual using this chip?)
First, SPARE_AREA_SKIP_BYTES is not the property of the hardware.
Rather, it is about the OOB layout, in other words, this parameter
is defined by software.
For example, U-Boot supports the Denali NAND driver.
The SPARE_AREA_SKIP_BYTES is a user-configurable parameter:
Your platform works with a zero in the SPARE_AREA_SKIP_BYTES register
because the NAND chip on the board was initialized with a zero
set to the SPARE_AREA_SKIP_BYTES register.
If the NAND chip had been initialized with 8
set to the SPARE_AREA_SKIP_BYTES register, it would have
been working with 8 to the SPARE_AREA_SKIP_BYTES.
The Boot ROM is the only (semi-)software that is unconfigurable by users,
so the value of SPARE_AREA_SKIP_BYTES should be aligned with
the boot ROM.
I recommend you to check the spec of the boot ROM.
(The maintainer of the platform, Dihn is CC'ed,
so I hope he will jump in)
Second, I doubt 0 is a good value for SPARE_AREA_SKIP_BYTES.
As explained in commit log, SPARE_AREA_SKIP_BYTES==0 means
the OOB is used for ECC without any offset.
So, the BBM marked in the factory will be destroyed.
> But in
> this case the patch assumes the default value 8 which is straight out wrong
> on this variant. Without this patch reverted all blocks of the nand flash are
> beeing marked bad :-(.
> When reverting the patch ba4a1b62a2d742df9e9c607ac53b3bf33496508f i can boot
> 4.19.10 again.
> With 5.0 the it goes further down the drain and i didn't manage to boot it
> even with the above patch reverted.
> I also tried 5.3-rc7 with the above patch reverted and the variable t_x dirty hacked to the
> value 0x1388 as i got the impression that the timing calculation is off too. I still get an
> interrupt error and boot failure:
git-bisect is a general solution to pin point the problem.
BTW, if you end up with hacking the clock frequency, something is already wrong.
denali->clk_rate, denali->clk_x_rate should be 50MHz, 200MHz, respectively.
If not, please check the clock driver and your DT.
> [ 0.817588] nand: device found, Manufacturer ID: 0x2c, Chip ID: 0xda
> [ 0.823946] nand: Micron MT29F2G08ABAEAWP
> [ 0.827965] nand: 256 MiB, SLC, erase size: 128 KiB, page size: 2048, OOB size: 64
> [ 1.887052] denali-nand-dt ff900000.nand: timeout while waiting for irq 0x1000
> [ 2.911056] denali-nand-dt ff900000.nand: timeout while waiting for irq 0x1000
> I have seen this https://lore.kernel.org/patchwork/patch/983055/ thread and
> this might fix at least the 4.19 boot problem.
> I would be really happy for hints how to get the Intel Cyclone V working again.
> Best regards
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