[PATCH V2] ARM: dts: imx7ulp-evk: Use APLL_PFD1 as usdhc's clock source
From: Anson Huang
Date: Wed Oct 30 2019 - 20:47:13 EST
i.MX7ULP does NOT support runtime switching clock source for PCC,
APLL_PFD1 by default is usdhc's clock source, so just use it
in kernel to avoid below kernel dump during kernel boot up and
make sure kernel can boot up with SD root file-system.
[ 3.035892] Loading compiled-in X.509 certificates
[ 3.136301] sdhci-esdhc-imx 40370000.mmc: Got CD GPIO
[ 3.242886] mmc0: Reset 0x1 never completed.
[ 3.247190] mmc0: sdhci: ============ SDHCI REGISTER DUMP ===========
[ 3.253751] mmc0: sdhci: Sys addr: 0x00000000 | Version: 0x00000002
[ 3.260218] mmc0: sdhci: Blk size: 0x00000200 | Blk cnt: 0x00000001
[ 3.266775] mmc0: sdhci: Argument: 0x00009a64 | Trn mode: 0x00000000
[ 3.273333] mmc0: sdhci: Present: 0x00088088 | Host ctl: 0x00000002
[ 3.279794] mmc0: sdhci: Power: 0x00000000 | Blk gap: 0x00000080
[ 3.286350] mmc0: sdhci: Wake-up: 0x00000008 | Clock: 0x0000007f
[ 3.292901] mmc0: sdhci: Timeout: 0x0000008c | Int stat: 0x00000000
[ 3.299364] mmc0: sdhci: Int enab: 0x007f010b | Sig enab: 0x00000000
[ 3.305918] mmc0: sdhci: ACmd stat: 0x00000000 | Slot int: 0x00008402
[ 3.312471] mmc0: sdhci: Caps: 0x07eb0000 | Caps_1: 0x0000b400
[ 3.318934] mmc0: sdhci: Cmd: 0x0000113a | Max curr: 0x00ffffff
[ 3.325488] mmc0: sdhci: Resp[0]: 0x00000900 | Resp[1]: 0x0039b37f
[ 3.332040] mmc0: sdhci: Resp[2]: 0x325b5900 | Resp[3]: 0x00400e00
[ 3.338501] mmc0: sdhci: Host ctl2: 0x00000000
[ 3.343051] mmc0: sdhci: ============================================
Fixes: 20434dc92c05 ("ARM: dts: imx: add common imx7ulp dtsi support")
Signed-off-by: Anson Huang <Anson.Huang@xxxxxxx>
Tested-by: Fabio Estevam <festevam@xxxxxxxxx>
---
Changes since V1:
- Add fixes tag.
---
arch/arm/boot/dts/imx7ulp-evk.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/imx7ulp-evk.dts b/arch/arm/boot/dts/imx7ulp-evk.dts
index f1093d2..a863a2b 100644
--- a/arch/arm/boot/dts/imx7ulp-evk.dts
+++ b/arch/arm/boot/dts/imx7ulp-evk.dts
@@ -78,7 +78,7 @@
&usdhc0 {
assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;
- assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
+ assigned-clock-parents = <&scg1 IMX7ULP_CLK_APLL_PFD1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc0>;
cd-gpios = <&gpio_ptc 10 GPIO_ACTIVE_LOW>;
--
2.7.4