Re: [PATCH v2 2/2] spi: cadence-quadpsi: Add support for the Cadence QSPI controller
From: kbuild test robot
Date: Fri Nov 01 2019 - 11:19:22 EST
Hi "Ramuthevar,Vadivel,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on spi/for-next]
[also build test WARNING on v5.4-rc5 next-20191031]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url: https://github.com/0day-ci/linux/commits/Ramuthevar-Vadivel-MuruganX/spi-cadence-quadpsi-Add-support-for-the-Cadence-QSPI-controller/20191101-174846
base: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next
config: x86_64-allyesconfig (attached as .config)
compiler: gcc-7 (Debian 7.4.0-14) 7.4.0
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@xxxxxxxxx>
All warnings (new ones prefixed by >>):
drivers/spi/spi-cadence-quadspi.c: In function 'cqspi_indirect_write_execute':
>> drivers/spi/spi-cadence-quadspi.c:606:7: warning: suggest parentheses around operand of '!' or change '&' to '&&' or '!' to '~' [-Wparentheses]
if (!(ret) & (*irq_status & CQSPI_IRQ_STATUS_ERR)) {
^~~~~~
At top level:
drivers/spi/spi-cadence-quadspi.c:359:12: warning: 'cqspi_direct_read_execute' defined but not used [-Wunused-function]
static int cqspi_direct_read_execute(struct struct_cqspi *cqspi, u8 *buf,
^~~~~~~~~~~~~~~~~~~~~~~~~
drivers/spi/spi-cadence-quadspi.c: In function 'cadence_qspi_delay':
>> drivers/spi/spi-cadence-quadspi.c:706:5: warning: 'tshsl' is used uninitialized in this function [-Wuninitialized]
if (tshsl < tsclk)
^
coccinelle warnings: (new ones prefixed by >>)
>> drivers/spi/spi-cadence-quadspi.c:1181:2-9: line 1181 is redundant because platform_get_irq() already prints an error
Please review and possibly fold the followup patch.
vim +606 drivers/spi/spi-cadence-quadspi.c
547
548 static int cqspi_indirect_write_execute(struct struct_cqspi *cqspi, u32 txlen,
549 const u8 *txbuf, u32 flash_type)
550 {
551 struct platform_device *pdev = cqspi->pdev;
552 struct cqspi_platform_data *pdata = pdev->dev.platform_data;
553 struct cqspi_flash_pdata *f_pdata =
554 &pdata->f_pdata[cqspi->current_cs];
555 void *reg_base = cqspi->iobase;
556 void *ahb_base = cqspi->qspi_ahb_virt;
557 u32 *irq_status = &cqspi->irq_status;
558 u32 page_size = f_pdata->page_size;
559 u32 write_bytes, timeout, reg = 0;
560 int remaining = (int)txlen;
561 int ret;
562
563 writel(0xa, reg_base + CQSPI_INDIRECT_TRIGGER_ADDR_RANGE_REG);
564 writel(0x0, reg_base + CQSPI_REG_INDIRECTWRWATERMARK);
565 reg = readl(reg_base + CQSPI_REG_SIZE);
566 reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB);
567 reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB);
568 reg |= (f_pdata->page_size << CQSPI_REG_SIZE_PAGE_LSB);
569 reg |= (f_pdata->block_size << CQSPI_REG_SIZE_BLOCK_LSB);
570 writel(reg, reg_base + CQSPI_REG_SIZE);
571
572 writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES);
573 writel(CQSPI_REG_SRAM_PARTITION_WR, reg_base + CQSPI_REG_SRAMPARTITION);
574 /* Clear all interrupts. */
575 writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
576 writel(CQSPI_IRQ_MASK_WR, reg_base + CQSPI_REG_IRQMASK);
577 reinit_completion(&cqspi->transfer_complete);
578 writel(CQSPI_REG_INDIRECTWR_START_MASK,
579 reg_base + CQSPI_REG_INDIRECTWR);
580
581 if (cqspi->wr_delay)
582 ndelay(cqspi->wr_delay);
583
584 while (remaining > 0) {
585 size_t write_words, mod_bytes;
586
587 write_bytes = remaining > page_size ? page_size : remaining;
588 write_words = write_bytes / 4;
589 mod_bytes = write_bytes % 4;
590
591 if (write_words) {
592 iowrite32_rep(ahb_base, txbuf, write_words);
593 txbuf += (write_words * 4);
594 }
595 if (mod_bytes) {
596 unsigned int temp = 0xFFFFFFFF;
597
598 memcpy(&temp, txbuf, mod_bytes);
599 iowrite32(temp, ahb_base);
600 txbuf += mod_bytes;
601 }
602 ret = wait_event_interruptible_timeout(cqspi->waitqueue,
603 *irq_status &
604 CQSPI_IRQ_MASK_WR,
605 CQSPI_TIMEOUT_MS);
> 606 if (!(ret) & (*irq_status & CQSPI_IRQ_STATUS_ERR)) {
607 ret = -ETIMEDOUT;
608 goto failwr;
609 } else {
610 ret = 0;
611 }
612 remaining -= write_bytes;
613
614 if (remaining < 0)
615 reinit_completion(&cqspi->transfer_complete);
616 }
617
618 /* Check indirect done status */
619 timeout = cadence_qspi_init_timeout(CQSPI_TIMEOUT_MS);
620 while (cadence_qspi_check_timeout(timeout)) {
621 reg = readl(reg_base + CQSPI_REG_INDIRECTWR);
622 if (reg & CQSPI_REG_INDIRECTWR_DONE_MASK)
623 break;
624 }
625 if (!(reg & CQSPI_REG_INDIRECTWR_DONE_MASK)) {
626 dev_err(&pdev->dev, "QSPI: Indirect write error %x", reg);
627 ret = -ETIMEDOUT;
628 goto failwr;
629 }
630
631 return 0;
632
633 failwr:
634 /* Disable interrupt. */
635 writel(0, reg_base + CQSPI_REG_IRQMASK);
636 /* Clear indirect completion status */
637 writel(CQSPI_REG_INDIRECTWR_DONE_MASK, reg_base + CQSPI_REG_INDIRECTWR);
638
639 /* Cancel the indirect write */
640 if (ret)
641 writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
642 reg_base + CQSPI_REG_INDIRECTWR);
643
644 return ret;
645 }
646
647 unsigned int cadence_qspi_is_controller_ready(void *reg_base)
648 {
649 return cadence_qspi_wait_idle(reg_base);
650 }
651
652 void cadence_qspi_controller_init(struct struct_cqspi *cqspi)
653 {
654 struct platform_device *pdev = cqspi->pdev;
655 struct cqspi_platform_data *pdata = pdev->dev.platform_data;
656
657 cadence_qspi_controller_enable(cqspi->iobase, 0);
658
659 /* Configure the remap address register, no remap */
660 writel(0, cqspi->iobase + CQSPI_REG_REMAP);
661 /* Disable all interrupts. */
662 writel(0, cqspi->iobase + CQSPI_REG_IRQMASK);
663
664 /* DAC is disabled for Intel LGM SOC */
665 if (!cqspi->dac_mode) {
666 enable_qspi_direct_access(cqspi->iobase, 0);
667 } else {
668 enable_qspi_direct_access(cqspi->iobase, 1);
669 /* TODO: for TI platform to be enabled */
670 cqspi_request_mmap_dma(cqspi);
671 }
672
673 /* Load indirect trigger address. */
674 writel(pdata->trigger_address,
675 cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER);
676
677 cadence_qspi_controller_enable(cqspi->iobase, 1);
678 }
679
680 unsigned int calculate_ticks_for_ns(u32 ref_clk_hz, u32 ns_val)
681 {
682 unsigned int ticks;
683
684 ticks = ref_clk_hz / 1000; /* kHz */
685 ticks = DIV_ROUND_UP(ticks * ns_val, 1000000);
686
687 return ticks;
688 }
689
690 void cadence_qspi_delay(struct struct_cqspi *cqspi, u32 ref_clk, u32 sclk_hz)
691 {
692 struct platform_device *pdev = cqspi->pdev;
693 struct cqspi_platform_data *pdata = pdev->dev.platform_data;
694 struct cqspi_flash_pdata *f_pdata = &pdata->f_pdata[cqspi->current_cs];
695 void __iomem *iobase = cqspi->iobase;
696 const unsigned int ref_clk_hz = pdata->master_ref_clk_hz;
697 unsigned int tshsl, tchsh, tslch, tsd2d;
698 unsigned int reg;
699 unsigned int tsclk;
700
701 cadence_qspi_controller_enable(cqspi->iobase, 0);
702 /* calculate the number of ref ticks for one sclk tick */
703 tsclk = DIV_ROUND_UP(ref_clk_hz, sclk_hz);
704
705 /* this particular value must be at least one sclk */
> 706 if (tshsl < tsclk)
707 tshsl = tsclk;
708
709 tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns);
710 tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns);
711 tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns);
712
713 reg = ((tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
714 << CQSPI_REG_DELAY_TSHSL_LSB);
715 reg |= ((tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
716 << CQSPI_REG_DELAY_TCHSH_LSB);
717 reg |= ((tslch & CQSPI_REG_DELAY_TSLCH_MASK)
718 << CQSPI_REG_DELAY_TSLCH_LSB);
719 reg |= ((tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
720 << CQSPI_REG_DELAY_TSD2D_LSB);
721 writel(reg, iobase + CQSPI_REG_DELAY);
722 cadence_qspi_controller_enable(cqspi->iobase, 1);
723 }
724
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