[PATCH v2 0/2] clk: Meson8/8b/8m2: fix the mali clock flags

[Martin Blumenstingl]

While playing with devfreq support for the lima driver I experienced
sporadic (random) system lockups. It turned out that this was in
certain cases when changing the mali clock.

The Amlogic vendor GPU platform driver (which is responsible for
changing the clock frequency) uses the following pattern when updating
the mali clock rate:
- at initialization: initialize the two mali_0 and mali_1 clock trees
  with a default setting and enable both clocks
- when changing the clock frequency:
-- set HHI_MALI_CLK_CNTL[31] to temporarily use the mali_1 clock output
-- update the mali_0 clock tree (set the mux, divider, etc.)
-- clear HHI_MALI_CLK_CNTL[31] to temporarily use the mali_0 clock
   output again

With the common clock framework we can even do better:
by setting CLK_SET_RATE_PARENT for the mali_0 and mali_1 output gates
we can force the common clock framework to update the "inactive" clock
and then switch to it's output.

I only tested this patch for a limited time only (approx. 2 hours).
So far I couldn't reproduce the sporadic system lockups with it.
However, broader testing would be great so I would like this to be
applied for -next.

Changes since v1 at [0]:
- extend the existing comment in patch #1 to describe how the glitch-
  free mux works with the CCF
- slightly updated the patch description of patch #1 to clarify that
  the "mali_0" or "mali_1" trees must not be changed while running
- add patch #2 to update the clk_set_rate() kerneldoc because we agreed
  that clk_set_rate() should do a root-to-leaf update (it does already,
  it's just not documented)


[0] https://patchwork.kernel.org/cover/11293177/


Martin Blumenstingl (2):
  clk: meson: meson8b: make the CCF use the glitch-free "mali" mux
  clk: clarify that clk_set_rate() does updates from top to bottom

 drivers/clk/meson/meson8b.c | 11 +++++++----
 include/linux/clk.h         |  3 +++
 2 files changed, 10 insertions(+), 4 deletions(-)

-- 
2.24.1