Re: [PATCH] x86/tsc: Unset TSC_KNOWN_FREQ and TSC_RELIABLE flags on Intel Bay Trail SoC

[Thomas Gleixner]

Vipul,

please always CC the relevant maintainers. Aside of that it's good
practice to CC the author of a particular commit you identified.

Vipul Kumar <vipulk0511@xxxxxxxxx> writes:

> From: Vipul Kumar <vipul_kumar@xxxxxxxxxx>
>
> 'commit f3a02ecebed7 ("x86/tsc: Set TSC_KNOWN_FREQ and TSC_RELIABLE
> flags on Intel Atom SoCs")', causing time drift for Bay trail SoC.
> These flags are set for SoCs having cpuid_level 0x15 or more.
> Bay trail is having cpuid_level 0xb.

Which is completely irrelevant. These CPUs read their frequency from
MSRs not from CPUID.

> So, unset both flags to make sure the clocksource calibration can
> be done.

That's going to break tons of ATOM SoC based systems which have neither
HPET not PIT.

Aside of that on some systems HPET/PIT based calibration is not really
more accurate than the MSR based frequency, quite the contrary.

Can you please provide detailed data about the problem you are trying to
solve? 'time drift' is pretty unspecific.

Thanks,

        tglx