Re: [PATCH v3 2/5] perf cs-etm: Continuously record last branch

From: Mike Leach
Date: Wed Feb 05 2020 - 11:01:27 EST


On Mon, 3 Feb 2020 at 01:52, Leo Yan <leo.yan@xxxxxxxxxx> wrote:
>
> Every time synthesize instruction sample, the last branch recording
> will be reset. This is fine if the instruction period is big enough,
> for example if use the option '--itrace=i100000', the last branch
> array is reset for every sample with 100000 instructions per period;
> before generate the next instruction sample, there has the sufficient
> packets coming to fill the last branch array.
>
> On the other hand, if set a very small period, the packets will be
> significantly reduced between two continuous instruction samples, thus
> the last branch array is almost empty for new instruction sample by
> frequently resetting.
>
> To allow the last branches to work properly for any instruction periods,
> this patch avoids to reset the last branch for every instruction sample
> and only reset it when flush the trace data. The last branches will
> be reset only for two cases, one is for trace starting, another case
> is for discontinuous trace; other cases can keep recording last branches
> for continuous instruction samples.
>
> Signed-off-by: Leo Yan <leo.yan@xxxxxxxxxx>
> ---
> tools/perf/util/cs-etm.c | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c
> index 3dd5ba34a2c2..3e28462609e7 100644
> --- a/tools/perf/util/cs-etm.c
> +++ b/tools/perf/util/cs-etm.c
> @@ -1153,9 +1153,6 @@ static int cs_etm__synth_instruction_sample(struct cs_etm_queue *etmq,
> "CS ETM Trace: failed to deliver instruction event, error %d\n",
> ret);
>
> - if (etm->synth_opts.last_branch)
> - cs_etm__reset_last_branch_rb(tidq);
> -
> return ret;
> }
>
> @@ -1488,6 +1485,10 @@ static int cs_etm__flush(struct cs_etm_queue *etmq,
> tidq->prev_packet = tmp;
> }
>
> + /* Reset last branches after flush the trace */
> + if (etm->synth_opts.last_branch)
> + cs_etm__reset_last_branch_rb(tidq);
> +
> return err;
> }
>
> --
> 2.17.1
>

Reviewed by: Mike Leach <mike.leach@xxxxxxxxxx>
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK